Abstract: A programmable delay circuit employs a relatively slow conventional silicon emitter-coupled transistor pair and a relatively fast silicon/germanium heterojunction emitter-coupled transistor pair. The bases of both transistor pairs are driven by an input signal to be delayed. The collectors of transistors of both pairs are linked to a voltage source through a pair of load resistors, with an output signal appearing across the collectors of both transistor pairs. A current source draws complementary adjustable load currents through the two transistor pairs. Although the sum of the two load currents is a constant, the relative amount of load current drawn though the two transistor pairs is adjustable.

Abstract: A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a host computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells. During a test the memory tester writes a bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective. The tester also counts of the number of memory cells of each row and column that are defective. After the test the counts are supplied to the host computer. When the host computer is unable to determine how to allocate the spare rows and columns from the counts alone, it requests the tester to process the data in the ECM to determine and supply the host computer with addresses of the defective memory cells.

Abstract: A network routing switch includes a crosspoint switch, a set of Ethernet I/O ports, a set of ATM I/O ports, a reassembly unit for converting ATM transmissions into Ethernet transmissions, and a segmentation unit for converting Ethernet transmissions into ATM transmissions. As an ATM I/O port receives cells of an ATM transmission from an external source it stores them until the transmission is complete and then sends the ATM transmission through the crosspoint switch either to a forwarding ATM port or to the reassembly unit depending on whether the ATM transmission is to be forwarded as an ATM or Ethernet transmission. When the reassembly unit receives an ATM transmission it converts it to an Ethernet transmission and forwards it through the crosspoint switch to a forwarding Ethernet I/O port.

Abstract: An apparatus for measuring a time interval between a start signal edge and a stop signal edge provides a stable clock signal as input to a delay line formed by a series of similar logic gates. The output signal of the last gate of the series is phase locked to the clock signal by adjusting a bias signal controlling the switching speed of all gates. The clock signal and the output signal of each gate form a set of phase distributed periodic timing signals applied to a start time measurement unit (TMU) and a similar stop TMU. The start TMU counts edges of one of the timing signals occurring between an edge of an arming signal and the start signal edge and generates output data representing a time delay between the arming signal and the start signal edge. The data represents the start delay as a whole and fractional number of clock signal periods by conveying the counter output and by indicating which of the timing signals had an edge most closely following the start signal edge.

Abstract: An integrated circuit (IC) tester includes a separate arbitrary waveform generator (AWG) for each input terminal of an IC to be tested. Each AWG generates a test signal input to the IC terminal that linearly ramps between discrete levels to approximate a smoothly varying waveform. Each AWG includes a digital-to-analog converter (DAC) formed by a set of N ramp generators, with each ramp generator producing output currents that ramp at adjustable rates between discrete levels in response to a change in state of an input waveform data bit. The output currents of all N ramp generators of the DAC, which have separately weighted magnitude levels, are summed and converted to a proportional voltage to produce the AWG's test signal.

Abstract: Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.

Abstract: A local area network routing switch for routing data transmissions between buses includes a set of input buffers, each for receiving and storing successive data transmissions arriving via a corresponding one of the bus. The switch also includes a set of output buffers for forwarding data transmissions outward via a corresponding bus, and a routing system for selectively routing data transmissions from the input buffers to the output buffers in response to routing requests from the input buffers. The routing system sends STATUS data to each input buffer indicating which output buffers are busy receiving data transmissions and which output buffers are idle. An input buffer makes a routing request only when it stores a data transmission to be forwarded to an idle output port. If its longest-stored data transmission is destined for a busy output port, it may send a routing request for a more recently stored data transmission if that data transmission is to be forwarded to an idle output buffer.

Abstract: A network switch routes data transmissions between network stations, each data transmission including network addresses of the source and destination network stations. The network switch includes a set of input/output (I/O) ports each for receiving data transmissions from and transmitting data transmissions to a subset of the network stations. Each I/O port is identified by a “physical” port ID and a “logical” port ID. While each I/O port's physical port ID is unique, all I/O ports that can route data to the same subset of network stations share the same logical port ID. Each I/O port receiving a data transmission from a network station sends its logical port ID and the network addresses included in the data transmission to an address translation system.

Abstract: A method of optimizing the frequency response of an interconnect system of the type which conveys high frequency signals between bond pads of separate integrated circuits (ICs) mounted on a printed circuit board (PCB) through inductive conductors, such as bond wires and package legs, and a trace on the surface of the PCB. To improve the interconnect system, capacitance is added to the trace and inductance is added to the conductors, with the added trace capacitance and conductor inductance being appropriately sized relative to one another and to various other interconnect system impedances to optimize the interconnect system impedance matching frequency response.

Abstract: An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits for performing a series of tests on an integrated circuit. The pattern generator is programmed to supply a sequence of pattern data as input to the tester circuits for controlling their operations during each test of the series. The pattern generator may also be programmed to interrupt the host computer before or during any test whenever it is necessary for the host computer to carry out an activity. The host computer may be programmed to respond to an interrupt by writing parameter control data into the tester circuits to reconfigure their operating characteristics, by acquiring test results from the tester circuits, or by directly controlling tester circuit operations during a test. When necessary to provide sufficient time for the host computer to carry out its task, the pattern generator may be programmed to temporarily suspend supplying pattern data to the tester circuits after sending an interrupt.

Abstract: A probe assembly contacts pins of a flat pack or other integrated circuit (IC) package having a body with a flat upper surface and a plurality of pins extending horizontally outward from the IC package body. The probe assembly includes a base that is bonded to the upper surface of the IC package body by a thermal-releasing adhesive when the base is pressed onto the IC package body. A set of probes (spring pins) extending downward from the base contact the IC pins when the base is bonded to the IC package body. The base includes a heating element for supplying heat to warm the adhesive and weaken the adhesive bond when the probe assembly is to be removed from the IC package. The heating element generates the heat in response to a current pulse passing through the heating element or alternatively receives the heat from an external source and conducts it to the adhesive.

Abstract: An integrated circuit (IC) tester includes set of tester channels, each for carrying out a test activity at a separate terminal of an IC device under test (DUT) during each cycle of a test. The tester also includes a disk drive having a removable disk for reading out scan or programming data to the tester channels during a test. Each tester channel includes an instruction memory for storing a set of instructions, and each tester channel executes its stored instructions during the test. Some of the instructions include VECTOR data directly indicating a particular test activity the tester channel is to carry out at a DUT terminal during a next test cycle. Others of the instructions tell the tester channel to acquire a particular number (N) of serial data bits as they are read out of the disk drive and to carry out an activity during each of the next N test cycles indicated by a state of a corresponding one of the N serial data bits.

Abstract: An integrated circuit (IC) tester includes a set of dual-purpose digital/analog channels. Each tester channel includes a driver capable of supplying either a digital or analog test signal input to an IC terminal and a receiver for digitizing and processing either an analog or digital IC output signal appearing at the DUT terminal to produce results data representing the behavior of that IC output signal during a test. A test is organized into a succession of test cycles, and before each test cycle a pattern generator within each channel produces data for controlling the behavior of the driver and receiver during the test cycle. The control data controls whether the driver is to produce an analog or a digital test signal, controls a magnitude or logic level to which the test signal is to be driven during the test cycle, and controls a time during the test cycle of any test signal state or magnitude changes.

Abstract: A signal source provides an output signal which can sweep over a broad frequency range in a well-controlled manner. The signal source includes a voltage controlled oscillator (VCO) producing the output signal and a waveform synthesizer producing a reference signal. The VCO output signal is phase locked to the reference signal. To make the VCO signal continuously sweep over a broad frequency range, the reference signal sweeps repeatedly over a narrow frequency range. During each sweep of the reference signal, the VCO frequency tracks an integer harmonic of the reference signal frequency. The frequency and phase of the reference signal for each successive sweep are abruptly reset at the beginning of each sweep selected such that the VCO signal frequency locks to another integer harmonic of the reference signal frequency and does not change.

Abstract: A thermometer-to-binary encoder includes a set of J input stage encoders E(1) through E(J) and an output encoder D, where J= 2.sup.K is an integer greater than 1. A set of digital input signals each representing a separate bit of a thermometer code T is grouped into J signal subsets representing further thermometer codes T(1) through T(J) providing inputs to a set of input stage encoders E(1) through E(J) respectively. Encoder E(J) produces an N-K+1 bit output binary code B(J) representing thermometer code T(J). Encoders E(1) through E(J-1) produce M-bit output binary codes G(1) through G(J-1), respectively, comprising the lower M bits of a binary code representing thermometer codes T(1) through T(J-1), respectively, where M is an integer greater than 1. Output encoder D processes codes G(1) through G(J-1) and B(J) to produce a set of digital output signals representing a binary code Y representing input thermometer code T.

Abstract: An instrument module development system for a computer-based instrument system, which system includes a chassis with slots for receiving various instrument modules and a system bus with a conventional computer bus for conveying commands and data between a host computer and the instrument modules and with additional lines for conveying control signals and data between the various instrument modules, has a module housing for insertion into one of the chassis slots, a development board mounted therein, and a serial input/output (SI/O) board. The development board includes a conventional computer processor, ROM, and computer bus interface circuits all interconnected by an intramodule bus. Firmware in the development board ROM enables the module to communicate with the host computer through the system bus. User developed applications firmware in the development board ROM enables the processor to communicate with and control a user provided instrument board via the intramodule bus.

Abstract: A data buffer includes parallel and serial data ports connected to one or more equipment modules that produce output data or respond to input commands. The data buffer also includes a serial control port communicating with a host computer. The data buffer receives and stores output data from the equipment modules via the data ports. The buffer configures each data port to match the data transfer protocol (baud rate, parity checking etc.) of the equipment module to which it is connected in response to input commands transmitted from the host computer via the control port. The host computer may also command the buffer to immediately route incoming data on one data port outward on one or more other selected data or control ports or to store incoming data for later transmission via a selected port in response to an input command. The host computer may additionally command the buffer to periodically transmit a stored data string outward on one or more designated data ports.

Abstract: A frame buffer memory controller allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller controls one or more pixel depth columns comprising one or more frame buffer memory chips per pixel. Each frame buffer memory controller listens on a display processor bus for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer for execution during the first free memory cycle.

Abstract: A system for testing electronic devices includes a waveform generator, a data acquisition system, and a computer. The waveform generator continuously generates a test signal having adjustable parameters set by the computer in response to user input. The data acquisition system acquires data representing the output of the device under test in response to the input signal and stores the last N acquired data values. The computer transfers a data sequence from the acquisition system to another memory and generates in a window on a terminal screen a wagveform display representing the stored data sequence. The computer also displays menu items referencing mathematical operations that may be performed on one or more data sequences. When a user selects one of the menu items, the computer prompts the user to select one or more windows containing waveform displays. Thereafter, the computer performs the selected operation on the data sequence controlling the waveform displays in the selected windows.

Abstract: An interface circuit permits a first bus master connected to a first bus to directly access a main memory connected to a second bus while maintaining coherency between corresponding data in the main memory and a cache memory used by a second bus master on the second bus. The interface circuit maps selected first bus addresses to corresponding second bus addresses such that when a bus master on the first bus attempts to read or write access one of the mapped first bus addresses, the bus interface circuit responds by read or write accessing a corresponding address in the memory on the second bus.