Patents Represented by Attorney David Aker
  • Patent number: 5521728
    Abstract: The present invention relates to the improvement in the frame area of the liquid display panel of a liquid crystal display device, and its object is to provide a liquid crystal display device which is enhanced in its blocking ability and the ability of the blocking area to prevent electrostatic failure. A blocking layer 12 is formed in a frame area 1 on TFT array substrate 3. The edge portions of the blocking layer 12 have overlapping areas 14 overlapping the edge portions of each of data lines 10, which are metal layers, with predetermined overlaping margin d as viewed from a direction perpendicular to the surface of the TFT array substrate 3. An insulation layer 16 is formed on the blocking layer 12 and the TFT array substrate 3. On the insulation a semiconductor layer 18 is formed. A plurality of data lines 10 is disposed on the semiconductor layer 18.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: May 28, 1996
    Assignee: International Business Machines Corporation
    Inventors: Manabu Kodate, Shinichi Kimura, Hidemine Yamanaka, Mitsuru Ikezaki
  • Patent number: 5489917
    Abstract: A liquid crystal display apparatus in normally-white mode in which gray scale display is obtained by providing different applied voltages corresponding to different gray scale levels, respectively, characterized in that in a curve showing the relationship between the applied voltage and light transmittance, the lowest applied voltage is set so as to be shifted in the direction of a monotonically decreasing region of the curve. The display simultaneously provides both good contrast ratios and good gradation at large viewing angles, and gray scale is not inverted.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: February 6, 1996
    Assignee: International Business Machines Corporation
    Inventors: Mitsuru Ikezaki, Shunji Suzuki, Hideo Takano
  • Patent number: 5469029
    Abstract: Deflection apparatus for a raster scanned cathode ray tube display comprises a flyback circuit (T2,T4,Ly,Df,Cf) including a switch (T2,T4) connected in series with an inductor (Ly). The switch (T4) is responsive to a line drive signal (LINE) to alternately open and close a current path through the inductor (Ly) between a first voltage level (B+) and a second voltage level (0V) lower than the first voltage level (B+) to generate a raster scan current signal in a deflection coil of the display. The amplitude of the raster scan signal is determined as a function of the first voltage level (B+) and the frequency of the line drive signal (LINE). A feedback circuit (D2,R3,D3,C2) connected to the switch (T4) generates a feedback signal (F) as a function of current flowing out of the switch (T4).
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: November 21, 1995
    Assignee: International Business Machines Corporation
    Inventors: Frederick S. Jackson, David Leaver
  • Patent number: 5467311
    Abstract: This invention relates generally to the accessing of random access access memory arrays and, more specifically to circuits and techniques for increasing the data valid time of such memory arrays without increasing either the access or cycle times of the array. This is accomplished by providing, during a read cycle, a read signal directly to an output driver and simultaneously providing, via a parallel path, a latch output to the same driver. The latch output is provided under control of the read signal and a returning portion of a clock pulse such that the latch output overlaps the direct read signal from a read/write amplifier. An output is provided from the latch until it is reset and may last well into the next read cycle even when a new read signal is present.
    Type: Grant
    Filed: July 31, 1990
    Date of Patent: November 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: Siegfried K. Wiedmann, Dieter F. G. Wendel
  • Patent number: 5461243
    Abstract: A structure with strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: October 24, 1995
    Assignee: International Business Machines Corporation
    Inventors: Bruce A. Ek, Subramanian S. Iyer, Philip M. Pitner, Adrian R. Powell, Manu J. Tejwani
  • Patent number: 5457415
    Abstract: A circuit for sampling monotonic input voltage changes and holding an output precisely derived from the sampled input change. The output change may be of the same polarity as the input, or inverted, and in the inverting mode of operation may exhibit highly accurate gain or attenuation. A single complementary metal-oxide-semiconductor (CMOS) embodiment may be configured to operate with positive or negative input changes and to present normal or inverted outputs, according to the application of various clock or control signals. Alternatively, subsets of that circuit provide subsets of the operating modes. The circuit operates by adding measured amounts of charge to, or removing it from a capacitor under the control of the input signal. Additional functional capabilities are capture and hold of input maximum or minimum, and accurate setting or restoration of the dc level of the output.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: October 10, 1995
    Assignee: International Business Machines Corporation
    Inventor: Eugene S. Schlig
  • Patent number: 5451535
    Abstract: A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate to the floating gate and by tunneling from the floating gate to the erase gate, respectively. The directional dielectric employed is a multilayered structured (MLS) oxide, where thin oxide and thin polycrystalline silicon form alternating layers. The layering is asymmetric: that is, either the uppermost or bottommost layer is thicker than the other layers. As a result of this structure, the oxide exhibits directionality, that is, the tunneling is easier in one direction than the reverse direction, and significantly enhances the tunneling phenomena (tunneling current can be observed at as low as 4.7 V). In addition, the MLS oxide can be fabricated having different dielectric constants.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: September 19, 1995
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Sang H. Dhong, Dieter P. E. Kern, Young H. Lee
  • Patent number: 5449984
    Abstract: This specification concerns cathode ray tube display apparatus comprises a cathode ray tube display screen (10). A beam generator (60,30) is provided for generating at least one electron beam in the cathode ray tube display screen (10) to produce a video image. Also provided is a line timebase circuit (40) for generating a line deflection signal to sequentially address the or each electron beam to successive pixels on the screen (10) in a line of a raster, and a frame timebase circuit (50) for generating an alternating frame deflection signal for sequentially addressing the or each electron beam to successive lines of the raster. The apparatus further comprises a standby circuit (110) connected to the line and frame timebase circuits (40,50).
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: September 12, 1995
    Assignee: International Business Machines Corporation
    Inventors: David Sawdon, John S. Beeteson, Peter Beanlands
  • Patent number: 5438342
    Abstract: A method and an apparatus for driving a liquid crystal display, in which flicker and cross talk are removed for arbitrary display patterns. The liquid crystal display has a plurality of scan lines, a plurality of data lines, and a plurality of pixels arranged in a matrix at the intersections of the scan and the data lines. The polarity of data signals outputted to the data lines is inverted for each occurrence of a pixel to be placed into a predetermined state. The predetermined state may be a dark state or a bright state of a binary display, or one of several levels of a display having more than two gray scale levels.
    Type: Grant
    Filed: May 15, 1992
    Date of Patent: August 1, 1995
    Assignee: International Business Machines Corporation
    Inventor: Hidefumi Yamaguchi
  • Patent number: 5436747
    Abstract: A liquid crystal display including row conductors and column conductors divided into odd conductor groups and even conductor groups. Each of the groups includes two or more adjacent conductors. A plurality of adjacent subpixels in a row direction and in a column direction form a single pixel. The adjacent subpixels in the single pixel are divided into a first subpixel group including adjacent subpixels arranged in the column direction and a second subpixel group including adjacent subpixels arranged in the column direction. The first subpixel group is connected to a first conductor of an odd conductor group and the second subpixel group is connected to a second conductor of the odd conductor group. An adjacent pixel in the row direction has a first subpixel group connected to one conductor of an even conductor group and a second subpixel group connected to a second conductor of the even conductor group.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: July 25, 1995
    Assignee: International Business Machines Corporation
    Inventor: Hiroshi Suzuki
  • Patent number: 5426430
    Abstract: A data line driver circuit having application in active matrix displays, such as thin-film transistor liquid crystal displays, uses charge metering techniques to achieve high precision and analog pipelining. Pipelining permits both the digital-analog conversion function and the presentation of the analog output to the display data line each to occupy most of the display's line time. The requirement of liquid crystals for periodic inversion of the net applied voltage is accommodated either by the circuits alone or with the display common electrode driven by a square wave.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: June 20, 1995
    Assignee: International Business Machines Corporation
    Inventor: Eugene S. Schlig
  • Patent number: 5420484
    Abstract: Deflection apparatus for a raster scanned cathode ray tube display comprises a ramp generator (210) for producing a current ramp signal synchronised to a raster synchronisation signal. A ramp regulator (230) is connected to the generator (210) for varying the amplitude of the scan signal as a function of the difference between a reference input and a feedback signal. A feedback circuit (220) connected to the generator (210) and to the regulator (230) for generating the feedback signal as a function of the amplitude and frequency of the line scan signal. A multiplier (250) is connected to the regulator and for varying the reference input as a function of an integer multiple of the frequency of the raster synchronisation signal. Any scan signal frequency component in the feedback signal is cancelled at the input to the regulator by introducing, via the multiplier (250), a scan signal frequency component to the reference input.
    Type: Grant
    Filed: April 5, 1993
    Date of Patent: May 30, 1995
    Assignee: International Business Machines Corporation
    Inventor: Andrew J. Morrish
  • Patent number: 5417791
    Abstract: A method of bonding faceplates (20) to VDU screens is provided in which an adhesive material is dispensed (80) onto a surface of either the faceplate or the VDU (40), the faceplate and the VDU are brought together (90) to force the adhesive material outwards to fill the gap between the surfaces, and the adhesive material layer (41) which is formed is then cured. In a first curing step (100), curing is carried out around the edges of the faceplate to form a seal around the edges. This first step may be carried out in a dedicated positioning tool. A later curing step (120) ensures that all of the adhesive material layer is eventually cured. Positioning (90) in the dedicated tool may use specific reference points on the faceplate and the VDU rather than relying on physical spacers, and may be carried out under servo control of a system for detecting the onset of undesirable gas entrapment conditions within the adhesive layer.
    Type: Grant
    Filed: June 20, 1994
    Date of Patent: May 23, 1995
    Assignee: International Business Machines Corporation
    Inventors: John Beeteson, Anthony C. Lowe
  • Patent number: 5416340
    Abstract: Leakage current due to light incident upon the semiconductor layer which forms the channel of a TFT is eliminated. An insulating layer is formed between one of source and drain electrodes and the semiconductor layer over a distance which is longer than a hole-electron recombination distance, from all the edges of at least one of the source and drain electrodes of the TFT so that it overlaps the semiconductor layer.
    Type: Grant
    Filed: June 9, 1993
    Date of Patent: May 16, 1995
    Assignee: International Business Machines Corporation
    Inventors: Toshihiko Yoshida, Masakazu Atsumi, Takeshi Matsumoto
  • Patent number: 5402149
    Abstract: To expand display data for a low-resolution matrix display apparatus to display data for a high-resolution matrix display apparatus without causing a reduction in the speed of processing and without requiring clocks of different frequencies. This is accomplished by providing intermediate value generating circuits for generating intermediate values of a plurality of adjacent display data according to an expansion ratio in a driver circuit of a matrix display apparatus and by also applying the outputs of the intermediate value generating circuits to the matrix display panel. Thus, the display data is expanded by the driver.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: March 28, 1995
    Assignee: International Business Machines Corporation
    Inventors: Atsuhiko Amagami, Nobuo Aruga
  • Patent number: 5400196
    Abstract: An apparatus (and a method for producing the same) for preventing internal vibrations produced as a result of rotary motion at a predetermined frequency within a device mounted in an enclosure from being translated into resulting rotary motion of the device comprises n vibration isolation mounts located between the device and the enclosure, said vibration isolation mounts having stiffness characteristics and being positioned so that rotational motion of the device at the frequency of the rotary motion is eliminated. The vibration isolation mounts are arranged and configured so that when the rotary motion produces linear and rotational forces, the net moment of all forces about the center of gravity of the device is equal to zero. The vibration isolation mounts may be isotropic. The isolation mounts may have different stiffness's. Three or more mounts may be used. Alternatively, the vibration isolation mounts may have the same stiffness's but their positions may be varied.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: March 21, 1995
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Moser, Arun Sharma, Muthuthamby Sri-Jayantha
  • Patent number: 5400028
    Abstract: A D/A converter which develops the analog output by summing binary-weighted packets of electrical charge. Charge metering techniques are used to generate and sum the charge packets. It is particularly suited to application in the data line driver circuits of thin-film transistor liquid crystal displays. Various embodiments use single or multiple charge packet generators, and the multiple version may generate the packets for the various bits simultaneously, For the highest speed, or else sequentially, for the largest voltage dynamic range.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: March 21, 1995
    Assignee: International Business Machines Corporation
    Inventor: Eugene S. Schlig
  • Patent number: 5392177
    Abstract: A sealed direct access storage device wherein a head is positioned for interaction with a storage medium in which the relative humidity is controlled by placing a predetermined amount of desiccant and a predetermined amount of water in the sealed volume of the device. At any given steady state temperature within a predetermined operating range the water vapor within the free space within the device and the water contained in the desiccant are in equilibrium and the relative humidity is controlled within acceptable limits.
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: February 21, 1995
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Chainer, Emanuel I. Cooper, Suryanarayan G. Hegde, Chandrasekhar Narayan
  • Patent number: 5388635
    Abstract: A cooling hat for transferring heat from a surface or plurality of heat generating components to a flowing fluid includes a coldsheet, a plurality of manifold layers and springs. The coldsheet is typically a medium-thin metal sheet usually with fine fins or grooves to readily transfer heat to a coolant. Each manifold layer is typically molded rubber with conduits for coolant supply and return. The conduits form a branched hierarchy. The fluid flow is highly parallel and streamlined which achieves ample flow with small hydraulic differential pressure. Springs gently urge the cooling hat against the thermal joints hence against the components. The hat can bend slightly to conform to a curved surface. Typically some compliance is provided by the hat, and other compliance is provided by a thermal joint between each component and the coldsheet. The system is highly self-aligned for counteracting variations.
    Type: Grant
    Filed: May 8, 1992
    Date of Patent: February 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Arthur R. Zingher
  • Patent number: 5389860
    Abstract: A focus control circuit for a CRT includes a focus bias voltage setting device for setting a focus bias voltage, a bias voltage control device for controlling the focus bias voltage and the focus bias voltage setting device in response to control information, a first amplifier for amplifying a luminance setting voltage with an amplification factor determined by an amplification factor control voltage and for supplying the amplified luminance setting voltage to a transistor, and a resistor network and a second amplifier for dividing a voltage applied to a control grid and applying it to the first amplifier as a control voltage.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: February 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: Masaki Kobayashi, Rieko Kataoka, Akihiro Funakoshi