Abstract: A tubular channeling unit including a grounded external metal sheathing and an internal longitudinal cavity, and method for laying such a tubular channeling unit by suspension on a high voltage aerial power line system including at least two towers supporting a set of high voltage electrical conductors suspended from the towers at a specified height above the ground and at a minimum predetermined safety level.
Abstract: An EID or RFID transponder having an encapsulant with an open end to allow insertion of the transponder circuitry and a phase changing material such as an epoxy used to both secure the circuitry of the transponder within the encapsulant and seal the open end of the encapsulant.
Abstract: A connector A includes a plurality of conductors. Each conductor consists of a contact 1, a terminal piece member 2, and a connecting conductor 3 connecting the contact 1 with the terminal piece member 2. The conductors are respectively held on a body 10 of the connector. The connecting conductors 3 are arranged in three layers in such a position relationship that can prevent them from short-circuiting each other and also can prevent a crosstalk from being produced between them. In this structure, the connecting conductors 3 are arranged in two or more levels, which makes it easier for the connector to be designed for prevention of the crosstalk when compared with a structure in which the connecting conductors 3 are arranged in one plane.
December 26, 1996
Date of Patent:
August 24, 1999
Matsushita Electric Works, Ltd.
Koji Ikeda, Yoshihiro Tanigawa, Shinji Morino, Koji Yamashita, Hirohisa Okuno, Takao Sase, Masahiko Amano
Abstract: A programmable controller includes a pipeline stage having a first stage IF for executing instruction fetching operations, a second stage ID/RF for decoding the instruction and for fetching data from a general-purpose register, a third stage EX for executing arithmetic and logic operations, data address calculations, or calculation of the effective address of a target branch, a fourth stage MEM for accessing to data memory, and a fifth stage WB/BPU for executing bit operations, writing operations with respect to the general-purpose register, or branching operations, are executed in a pipelined manner. Simplification of hardware and control, and facilitation of formation of a pipeline into multiple stages are realized as a result of a pipeline structure being formed into a unified instruction structure.