Abstract: A data communications controller, for use intermediately between a data processor and a data communications link such as a modem driven land line, relieves the data processor of time-consuming supervisory and data preparation tasks, normally associated with the use of a data link, by means of a block loadable transmit queue, an automatic cyclic redundancy check generator, an automatic time fill generator and a parity generator, a block unloadable receive queue, an automatic character translator, an automatic character monitor and a received serial bit queue in conjunction with a byte synchronizing detector, the operation or non-operation of each of the above elements and, if operational, the manner of that operation, being selectable by commands from the data processor, the commands from the data processor being intermingled with but distinguishable from data to be sent over the data link.

Abstract: A three beam laser optical system comprising a writing beam and two reading beams all incident on the same track of a rotating disk optical recording medium. One of the reading beams is incident on the track ahead of the writing beam so as to serve as a read-before-write beam, while the other reading beam is incident on the track behind the recording beam so as to serve as a read-after-write beam. The read-before-write beam is used during the recording of data to provide an advance indication as to whether there is previously recorded data ahead of the writing beam, in which case the recording operation is interrupted to prevent an overwrite error. The read-after-write beam is used during recording to check the accuracy of the recording operation.

Abstract: A pipelined microprogrammed data processing system is provided having a three-stage pipelined architecture implemented so as to in effect provide for the execution of a plurality of microinstructions using three separate processors operating 120 degrees out of phase with one another and sharing the same physical hardware. Synchronized microinstruction tasking and dynamic resource allocation are also provided in the system to provide both multiprogramming and multiprocessing on a microinstruction level.

Abstract: A microprogrammed data processing system is provided in which each high level instruction is performed by one or more tasks, each task being in turn performed by executing one or more task microinstructions in a microprogrammed manner. Dynamic resource allocation is provided by employing a plurality of dynamically allocatable registers whose free and use states are continuously monitored in an allocation register. The outputs of the allocation register are used as an address for a register allocation memory which is mapped so as to identify a particular group of free registers which are available for assignment for each new task in response to the allocation register address.

Abstract: An improved driver circuit for transistor power switches, which allows operation of the power transistor at high output power and at a duty range from zero to 100 percent without the previously large switching losses. This new driver circuit uses a constant current source which forces base current into the power transistor.

Abstract: A high density optical storage system employing a laser beam for reading data in a track on a rotating optical disk containing a large number of closely spaced concentric tracks. When a short seek operation is to be provided, track following is temporarily suspended for an appropriate time period during which specially shaped waveform is applied to the galvanometer-controlled mirror in the path of the beam. This specially shaped waveform is a doublet comprising a pulse of one polarity followed by a pulse of the opposite polarity. The duration and amplitude of these opposite polarity pulses are chosen based on the number of tracks that the beam is to be moved and the mechanical characteristics of the system so that the galvanometer mirror will accurately move the beam the requested number of tracks. After movement of the beam has been completed, operation automatically returns to track following.

Abstract: A digital memory system comprises a wafer full of uncomitted but interconnectable memory cells and a controller acting as an interface between the wafer and a host system. Each cell comprises input logic to allow coupling thereto from just one other neighboring cell and output logic allowing a cell to be commanded by the controller to couple to any selectable one other neighboring cell not already so coupled to. The controller accesses the wafer via a port and successively tests and couples cells from the port to form a chain of memory cells. Each cell comprises a plurality of individually selectably usable data storage loops and allows a cell to be used even if the loops are not fully functional by the provision of through-passing data transfer path.

Abstract: A monitor (9) for determining the amount of metal which has been removed during the course of a chemical etching process comprises an etch resistant substrate (10) whereon are affixed a plurality of metal foil areas (12A to 12H) each with its own, known substantially uniform thickness prior to the start of the etching process, indication of the progressive depth of etching being provided by which out of the plurality of areas of foil (12A to 12H) remain at any particular time after the commencement of etching.

Abstract: A servomechanism avoids load-damaging conditions by being shut down whenever a power-amplifier saturation detector fails to detect a change in the saturation state of the power amplifier in response to the periodic and momentary replacement of the demand signal by one or other of two test signals, which of the two test signals is selected being dependent upon the expected direction of possible saturation of the power amplifier and the polarity of both test signals being the same as the polarity of the applied demand signal.

Abstract: N-way microprogram branching is employed in conjunction with a specially organized multiple-chip microinstruction memory in a manner which makes it possible to divide the accessing of the memory into two separate operations which can be performed simultaneously and in parallel, thereby significantly reducing the time required for accessing the memory.

Abstract: A memory system includes an integrated circuit comprising a plurality of testably interconnectable cells in a tessellation on a semiconducting wafer. A controller for acting as an interface between the wafer and some host system is coupled to the wafer via a port formed by the omission of one of the cells from the tessellation. Each cell comprises plural-bit data storage registers each having an associated single-bit access register and an associated single-bit control register. During a growth phase a state machine co-operates with global signals and test data from the controller to operate data-testing and inter-register coupling logic to form a branched-labyrinth of tested cells characterized by rapid growth and efficient incorporation of functional cells. After growth data is transferred between the chain of data storage registers and the chain of access registers so formed dependently upon the contents of an associated chain of control registers.

Abstract: A printer-processor is used to print multi-ply business forms. The printer processor uses paper from a paper roll and uses an absorptive ink which dries substantially by absorption. The ink stays in liquid form during stopping and starting periods of the printer processor. The ink is also thixotropic so as to remain at proper film thickness on the printing surfaces of the printer processor at operational speeds or when stopped. The absorptive thixotropic ink enables the printer processor to deliver to the collator webs of paper having an uninterrupted sequence of images of uniform quality. The paper has one continuous path between the printer processor and the manifold forms collator. To enable the printer processor to print all common form sizes from small cylinders, a unique cluster of gears arrangement is attached to the impression cylinder of the printing unit. This cluster contains gears with circular pitches which are the increments which are evenly divisible into the common form sizes.

Abstract: A decoder decodes and accurately scales so-called "tribit" servo signals after the receipt of only one tribit pattern without the use of A.G.C. by storing the peak values of the position indicating pulses the capacitors in first and second peak-and-hold circuits and thereafter discharging both capacitors with the same time constant, activating a sample-and-hold circuit to hold the value of the output of a difference amplifier at the instant when the output of a summing amplifier falls below a predetermined value.

Abstract: Multi-phase subroutine control apparatus for use in a data processing system which provides for the concurrent execution of a plurality of tasks in a multiprogramming and multiprocessing environment. Subrouting control operations are staged so as to share common hardware in a manner which in effect provides a plurality of phased concurrently operating subroutine control circuits wherein each circuit provides control for a different one of a plurality of concurrently executing tasks. The common subroutine hardware includes a multi-level stack for each task and a fast access return address register which permits a return address to be rapidly made available when required during execution of a task.

Abstract: A rotary, self contained, unitary, modular detack mechanism for cantilever pivotal mounting wherein an epicyclic gear assembly operably connected to a continuously rotating source of motion is caused to advance a portion of adhesive material from a supply to a take-up receptacle over a peripheral projection on the mechanism in timed synchronism with a solenoid actuated cam follower effective to rotate the mechanism concurrently raising and lowering the same into momentary contact with and being detacked, stripper members straddling the mechanism strip the item from the adhesive.

Abstract: Subroutine control apparatus for providing shared subroutine control for a plurality of executing tasks. Multiple levels of subroutine entry are provided for each task by employing a plurality of selectably accessible stacks, one for each task, along with corresponding pointer registers. These provide storage for a plurality of return addresses as required for each task during task performance. In addition, an updatable significantly faster access register is provided for each task for storing its most recent return address so as to permit return addresses to be rapidly made available when an executing task reaches the end of a subroutine.

Abstract: A data processing system, having a volatile main memory prepares for power supply failure, at the first instance of power supply potential falling below a predetermined limit, by readying its current task for restart, data-saving by storing the contents of volatile, processor registers in the main memory, and completing any non-postponable tasks. If power deficiency lasts for longer than a predetermined period, the memory is maintained by a battery power source if and only if data-saving has been completed. Restoration of power during the predetermined period causes instant reversal and restart, but after the elapse of the predetermined period, causes reversal and restart if and only if a data save has been completed, otherwise causing reinitialization.

Abstract: Address generating apparatus which uses narrow data paths for generating a wide logical address and which also provides for programs to access very large shared data structures outside their normally available addressing range and over an extended range of addresses. Selective indexed addressing is employed for providing index data which is also used for deriving variable dimension override data. During address generation, selected index data is added to a displacement provided by an instruction for deriving a dimension override value as well as an offset. The derived dimension override value is used to selectively access an address locating entry in a table of entries corresponding to the applicable program. The resulting accessed address locating entry is in turn used to determine the particular portion of memory against which the offset is to be applied.

Abstract: The disclosure is of a glass composition including PbO, SiO.sub.2, B.sub.2 O.sub.3, BaO, ZnO, Al.sub.2 O.sub.3 and Na.sub.2 O. The glass is used as an insulating layer in gas-filled display panels including an electrode which is insulated from the gas therein.

Abstract: An optical data storage system employing a data-modulated writing laser beam and a non-erasing reading laser beam of predetermined wavelength along with an improved optical medium comprised of multiple layers whose optical characteristics and thicknesses are chosen in conjunction with the writing and reading laser beams to provide an anti-reflection condition for unrecorded portions of the medium and a relatively high reflectivity for recorded portions of the optical medium. A preferred optical medium includes a highly reflective aluminum layer, a fluorinated hydrocarbon polymer spacer layer overlaying the reflective layer, a nucleation layer overlaying the spacer layer and also serving as a heat insulator therefor, and a gold absorber layer overlaying the nucleation layer.