Abstract: Briefly, in accordance with one embodiment of the invention, a bootstrap circuit comprises a pair of drivers coupled together so as to form a bootstrap node and a bipolar transistor coupled to the bootstrap node. A method of using a bipolar transistor in such a bootstrap circuit comprises the step of applying a voltage signal to the input ports of the drivers, the voltage signal having a magnitude sufficient to activate the bipolar transistor.

Abstract: A method and fixture for laser bar facet coating are disclosed. A holder for securing devices having surfaces for coating includes first and second channels. A plurality of web slats are received in the channels. The web slats have first and second ends and first and second device engaging surfaces. The ends of the web slats are received in respective channels. The ends of the web slats cooperate with the ends of adjacent web slats. The web slats are secured at one end of the channels and otherwise are movable along the channels between an open position to receive devices therebetween for coating and a closed position in which edges of the web slats engage the devices received therebetween for coating. A bias member may be used to retain the web slats in the closed position gripping the devices for coating. In another embodiment, the invention provides a method for coating surfaces of substantially parallelepiped devices.

Abstract: A phase lock detector circuit is disclosed that generates delayed versions of both a reference clock signal and a synthesized clock signal. From the delayed signals, first and second control signals that are pulses are generated. The pulses are passed through respective delays of predetermined durations and then clocked into respective shift registers by the latched signal of the opposite input. The shift register outputs are logically combined and shifted into a third shift register. Outputs from the third shift register are logically combined to ascertain whether a phase-lock loop is phase lock. The lock detector circuit may include a lock-out circuit to disable the phase lock detector circuit upon detecting phase lock.

Abstract: There is disclosed a first adder subtractor combines the largest positive number or largest negative number capable of being represented by the number of bits in the datapath, as determined by the sign of an input to a second adder with a first input to generate a first potential sum. A second adder operating in parallel with the first adder combines first, second and third inputs to generate a second potential sum. An overflow detector combines the first and second inputs of the second adder to determine if there is an overflow. If an overflow is not present, a multiplexer selects the output of the second adder as the output to be saturated. If an overflow is present, the multiplexer selects the output from the first adder as the output to be saturated.

Abstract: There is disclosed a converter for summing inputs includes first, second, third and fourth adders. Each of the adders is adapted to receive a carry-in and to provide as outputs a carry-out and a sum output. Each adder has an associated partial product generated in proximity thereto. The adders are interconnected such that the associated partial product of the first and second adders provide additional inputs to the first adder. The associated partial products of the third and fourth adder provide additional inputs to the second adder. The sum output of the first and second adders provide additional input to the third adder. A sum input to the converter and the sum output of the third adder provide additional inputs to the fourth adder. The output of the fourth adder is the output of the converter.

Abstract: There is disclosed an integrated circuit including a programmable driver circuit having first and second transistors. Each of the first and second transistors has first, second and third terminals. The first terminal of each of the first and second transistors are coupled together to form an input node. The second terminal of the first transistor is coupled to a power node. A third terminal of the first transistor is coupled to a first intermediate node. The second terminal of the second transistor is coupled to a second intermediate node. The third terminal of the second transistor is coupled to a reference potential. A first switch having at least one input is coupled between the first and second intermediate nodes. Third and fourth transistors each having first, second and third terminals. The first terminal of the third transistor is coupled to a third intermediate node. The first terminal of the fourth transistor is coupled to the second intermediate node.

Abstract: There is disclosed a method and apparatus for computing branch metrics that are combinations of autocorrelation and cross correlation terms are constructed by first calculating and storing components of the autocorrelation and cross correlation terms at a symbol instant. Once calculated and stored, predetermined ones of the autocorrelation components and the cross correlation components are selected. The selected autocorrelation components and cross correlation components, or their inverse as predetermined, are combined to produce a branch metric. Other predetermined combinations of the stored components of autocorrelation and cross correlation terms, or their inverse, are combined to produce other branch metrics at the same symbol instant. All branch metrics associated with the symbol instant can be calculated in this manner.

Abstract: There is disclosed a method of positioning an optical subassembly for testing includes positioning an optical subassembly within a capture zone on a support surface of a test fixture. At least two probes engage surfaces of respective ones of precisely located fiducials in a surface of the optical subassembly. A third probe contacts a surface of the optical subassembly, which in a preferred embodiment may be another fiducial in the surface of the optical subassembly. Upon engagement of the probes with surfaces of respective fiducials and movement of the probes further into respective fiducials, the optical subassembly is translated into more precise alignment with optics of the test fixture.

Abstract: A system for scrambling a video signal, wherein multiple modes of scrambling are available, including (i) line reversal, (ii) line inversion, (iii) line permutation, and (iv) block permutation. The invention changes the combination of modes used as time progresses. In addition, particular modes can be implemented, or suppressed, in response to such factors as (i) noise in the transmission channel and (ii) amount of motion within the video image.

Abstract: There is disclosed an integrated circuit includes an output driver circuit providing control of transition time from one state to another. The output driver includes first and second input transistors coupled to an input node at which data is received. First and second output transistors are coupled to an output node at which the data is presented when the output driver is enabled. The first input transistor is coupled to the first output transistor defining a first node. The second input transistor is coupled to the second output transistor defining a second node. First and second switching circuits are coupled between the first node and the second node. The first switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node.

Abstract: There is disclosed an integrated circuit including a digital processor having EEPROM and a control register. The digital processor is capable of receiving data to be programmed into the EEPROM and is capable of programming the data into the EEPROM. The digital processor includes a control register for receiving bits to control a write line and an erase line. The digital processor also includes a processor core coupled to the control register by a data bus, the digital processor is coupled to the EEPROM by a ROM address bus and a RAM data bus. The EEPROM memory location identified by the ROM address bus is programmed to retain data latched onto the RAM data bus. This is achieved by the digital processor writing control bits to the control register to enable the write line for a write operation of sufficient duration to assure that the data on the RAM data bus is retained in the EEPROM memory address that is enabled.

Abstract: An application-specific single chip digital processor having flexible design expansion capability with minimal impact on the performance of a processor core. The processor core has an ALU and a register file (accumulators). The output of the ALU is connected to a multiplexer whose output is connected to the input of the register file. The output of the register file connects to one input of the ALU. A function unit, separate from the core, has an input connected to the output of the register file and an output connected to another input to the multiplexer. The core operates with a predefined instruction set. The function unit, which may be redesigned depending on the application, operates with a reserved (uncommitted) instruction set under control of the core.

Abstract: Briefly, in accordance with one embodiment of the invention, a circuit comprises: a sigma-delta modulator including an input signal port, an output signal port, and a signal path. The signal path includes a feedforward signal path and a feedback signal path. The signal path is adapted to be coupled to a dither signal and the circuit is adapted to adjust the dither signal substantially in accordance with a signal applied to the input signal port. In accordance with another embodiment of the invention, a method of improving the stability of a sigma-delta modulator, the modulator employing dither, comprises the steps of: applying a signal to the input port of the sigma-delta modulator; applying a dither signal to the signal path of the sigma-delta modulator; and adjusting the dither signal applied substantially in accordance with the signal applied to the input port.

Abstract: There is disclosed an integrated circuit including a resistor string comprising a plurality of resistors. The resistor string includes a first array of resistors for determining a predetermined number, M, of most significant bits, and a second array of resistors for determining a predetermined number, L, of least significant bits. Each of the first and second arrays of resistors define intermediate taps. First and second arrays of switching transistors are coupled to the respective taps in respective first and second arrays of resistors. Switches in the first array of switching transistors are coupled between a respective intermediate tap in the first array of resistors and a first output node. Transistors in a second array of switching transistors are coupled between a respective intermediate tap in the second array of resistors and a second output node.

Abstract: There is an equalizer or a receiver including an equalizer which has means to factor detected symbols transmitted over a transmission channel into a magnitude portion and a repetitive phase portion. The receiver further has means to generate modified tap weights by multiplying the repetitive phase portion by tap weights representative of the channel. Modified tap weights are generated by multiplying the repetitive phase portion by tap weights representative of the channel. The modified tap weights are convolved with bits of possible states to generate possible transmitted symbols. A maximum likelihood sequence estimation is performed on the possible transmitted symbols comparing each possible transmitted symbol to a received symbol to generate an MLSE detected symbol. The detected symbol is multiplied by a rotating vector to generate a decoded symbol.

Abstract: There is disclosed an integrated circuit in accordance with an illustrative embodiment of the present invention, method of operating a digital converter includes a capacitor on which a sampled analog signal is stored. The capacitor has a first element and a second element. The second element is capable of being referenced to more than one potential. The analog-to-digital converter includes a voltage gradient and a comparator for comparing the sampled analog signal to selected voltages of the voltage gradient to indicate which is larger. Each of the voltages developed along the voltage gradient corresponds to a digital code representative of the voltage.

Abstract: An integrated circuit for converting an analog signal to a digital signal includes a resistor string comprised of a plurality of serially coupled resistors coupled between a high voltage reference and a low voltage reference. Intermediate taps are defined at the junctions of the resistors in the resistor string. At least one comparator has first and second inputs and an output. The first input of the comparator is capable of being selectively coupled to preselected ones of the intermediate taps. The second input is capable of being switched between an unknown analog input in conversion mode and a predetermined tap that provides a nominal voltage at the second input in calibration mode. A selection circuit for sequencing through the preselected ones of the intermediate taps selects one of the preselected ones of the intermediate taps as a selected tap for compensating for the offset of the at least one comparator. The selection circuit stores the selected tap for subsequent use during operation of the circuit.

Abstract: An echo canceller system includes first and second echo cancellers. Each echo canceller includes a foreground filter and an adaptive background filter, with the foreground filter providing the actual echo cancellation and the background filter updating the foreground filter. The echo canceller system also includes send and receive paths, a shared coefficient memory, and a controller for switching the shared coefficient memory between background filters in response to signals along the send and receive paths. The switching includes resetting the shared coefficient memory to prevent any transfer of filter coefficients between the background filters. The background filters operate one at a time, depending on which background filter has access to the shared coefficient memory, while the foreground filters operate simultaneously.

Abstract: An echo canceller includes receive and send paths each having an input and output port, a first non-adaptive filter with first filter coefficients for generating a first replica signal in response to a receive input signal, a second adaptive filter with second filter coefficients for generating a second replica signal in response to the receive input signal, a first subtracter for generating a send output signal representing a difference between a send input signal and the first replica signal, a second subtracter for generating an error signal representing a difference between the send output signal and the second replica signal, and a controller for replacing the first filter coefficients by the sum of the first and second filter coefficients and for resetting the second filter coefficients in response to a calculation that includes a first quantity associated with the send output signal and a second quantity associated with the error signal.

Abstract: A data converter for converting a signal either from analog form to digital form or from digital form to analog form includes a storage register. The storage register receives and temporarily stores digital data samples. The digital data samples are transferable out of the storage register in the same sequence in which they were received. A digital signal processor coupled to the storage register is interruptible to transferred digital data samples either to or from the storage register. In this manner, the digital signal processor transfers multiple digital data samples either to or from the storage register during each interrupt rather than transferring a single data sample per interrupt, thereby reducing the number of interrupts necessary to transfer a given number of digital data samples.