Abstract: A method for programming non-volatile row redundancy memory registers. Each register is associated with a respective pair of redundancy row and each one programmable to store in two subsets of a set of memory cells a pair of addresses of a respective pair of adjacent defective rows. Each memory register is supplied with row address signals and with a respective selection signal belonging to a set of column address signals.

Abstract: A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device. The circuit includes an operational amplifier with a first input coupled to a reference voltage, a second input coupled to the negative word line voltage, and an output controlling a voltage regulation branch connected between an external power supply and the negative word line voltage, to provide a regulation current for regulating the negative word line voltage. The output of the operational amplifier also controls a voltage sensing branch, connected between the external power supply and the negative word line voltage, to provide a sensing signal coupled to the second input of the operational amplifier.

Abstract: A driver circuit for an electronically commutated electric motor, in particular stepping motor, having one full bridge circuit (I, II) per motor winding (L1, L2), a current sensor resistor (R), a measured value storage device (C5) and a regulator circuit (OP1-OP5) for regulating, during part of the driver phases, the total current flowing through the driver circuit in such a way that this current matches a total current value flowing outside the regulating phases and stored in the storage circuit (C5), in order to prevent alternating components in the total current fed via the supply voltage lines.

Abstract: A memory array has a floating gate transistor cell connected to a bit line and a bit line driver circuit comprising a variable impedance FET and an active load powering the bit line from a supply node. A control circuit selects a voltage applied to the gate of the variable impedance FET to control the bit line voltage, e.g., in dependence on parameters of the cell.

Abstract: In an integrated circuit for programming a memory cell in a non-volatile memory register which is associated with a memory matrix wherein the non-volatile memory register is used to store a redundancy address, the memory cell has at least one programmable non-volatile memory element having a control electrode and a data electrode and is suitable to store one bit of information. A load circuit associated to the memory element reads the information stored therein. The integrated circuit has switching means connected in series between the data electrode and a respective address signal line of an address signal bus which also supplies a decoding circuitry of the memory matrix.

Abstract: A oscillator having two synchronized oscillator rings is described. Synchronization is accomplished by circuitry connected between the outputs of two aligned stages in coupled oscillator rings, the circuitry being operable to maintain outputs of the stages 180.degree. apart in phase.

Abstract: A DC-to-DC (buck) converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit related to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.

Abstract: A converter employs a comparator sensing the current through an output diode, for generating a confirmation signal of an OFF state of the switch until the discharge current of the inductor toward the user circuit and the external filter capacitance has become null, thus ensuring the operation in a discontinuous mode under any condition. A turn-off signal of the switch is provided by another comparator which, instead of the voltage on a sensing resistance connected in series with the switch, may sense the voltage across the switch itself. This latter embodiment is particularly suited in case of an output MOS transistor and the circuit comprises means for masking for a preset period of time the turn-off signal produced by said comparator, in order to allow a predefined turn-on phase of the switch. Enabling of the turn-on of the switch is conventionally provided by a dedicated (third) comparator of the output voltage.

Abstract: An integrated telephone interface circuit for driving a telephone line includes a line current sensor and a phase converter, both associated with an output stage connected to the telephone line. The circuit is equipped with a protection device against the generation of spurious signals including a comparator connected between the converter and the output stage, a control and monitoring circuit linked operatively to an output of the comparator, and a plurality of switches associated with the input side of the converter, as well as with the current sensor and the output stage. The switches are linked operatively to respective outputs of the control and monitoring circuit to reverse polarity of the line supply upon a predetermined threshold value for the comparator being exceeded.

Abstract: A monolithically integrated AC coupling circuit is presented for DC uncoupling and AC coupling (typically in telephone applications) to an input signal. The AC coupler includes a high-pass filter having a first pole at a frequency well below a frequency of interest and a zero at zero frequency. The AC coupler also includes a pole/zero doublet between the frequency of the first pole and the frequency of interest. The frequency of the first pole for a specified error is increased by addition of the doublet. Because the frequency of the first pole is increased, the size of the required capacitors is decreased, enabling integration. An implementation of the circuit using switched capacitor techniques is described. An alternative circuit employing a unit gain interface is presented. The alternative circuit reduces the dynamic range and driving voltage requirements of its field-effect transistors.

Abstract: A quadrature oscillator is provided constructed of NOR gates in the manner of a non-linear circuit which is inherently unstable and which cycles sequentially through four distinct states at a rate determined by the constitution of the NOR gates. The quadrature oscillator includes first and second stages that each include first and second NOR gates. The output of the first NOR gate of the first stage is connected as an input to the second NOR gate of each of the first and second stages. The output of the second NOR gate of the first stage is connected as an input to the first NOR gate of each of the first and second stages. The output of the first NOR gate of the second stage is connected as an input to the first NOR gate of the first stage and the second NOR gate of the second stage. The output of the second NOR gate of the second stage is connected as and input to the second NOR gate of the first stage and the first NOR gate of the second stage.

Abstract: A protection circuit (1) comprising a first and second supply line at a first and second supply voltage respectively; a reference voltage source; a comparator connected to the first supply line and the source; and a switch controlled by the comparator via a control terminal and located between the second supply line and the output of the circuit. To reduce static consumption of the comparator under normal operating conditions, the circuit comprises enabling control elements connected to the two supply lines and to the comparator for disabling the comparator and turning on the switch when the two supply voltages differ by a value below a predetermined threshold, but are greater than a reference value.

Abstract: The PLA, which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator which generates a monostable succession of read enabling signals on receiving a predetermined switching edge of an external clock signal. The clock generator enables evaluation of the AND and OR planes of the PLA and subsequently storage of the results through sections duplicating the propagation delays of the signals in the corresponding parts of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.

Abstract: Redundancy circuitry layout for a semiconductor memory device comprises an array of programmable non-volatile memory elements for storing the addresses of detective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines. The redundancy circuitry layout is divided into identical layout strips which are perpendicular to the array of memory elements and which each comprise first and a second strip sides located at opposite sides of the array of memory elements, the first strip side containing at least one programmable non-volatile memory register of a first plurality for the selection or redundancy bit lines and being crossed by a column address signal bus running parallel to the array or memory elements, the second strip side containing one programmable non-volatile memory register of a second plurality for the selection or redundancy word lines and being crossed by a row address signal bus running parallel to the array of memory elements.

Abstract: A scheme for altering checking information in a message packet intended to be transmitted between computers is described. In this scheme, when an information portion of the packet is altered, checking bits contained in the packets are altered in dependence only on the set of checking bits in the message packet before modification of the information portion and on the modifications to the information portion. Thus, it is not necessary to generate new checking bits from a modified information portion.

Abstract: A method for measuring the degree of planarity in an integrated circuit includes depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity. An integrated circuit containing a measurement portion of conductive film and a reference portion of conductive film is described.