Abstract: A method and apparatus for molding a video display screen bezel to a video display device, such as a CRT, is disclosed. The bezel is molded in such a way as to eliminate the need for fasteners between the bezel and the CRT and between the bezel and a housing or some other structural support. The molded bezel also prevents any undesirable shifting of the CRT with respect to the bezel due to accidental dynamic loads. The molding material conforms to the surface of the CRT compensating for any dimensional variations in the CRT while minimizing the size of the bezel. Molded within the bezel is a compensating means which absorbs stresses generated by the molding material both during and following the molding process which might otherwise be exerted on the CRT.

Abstract: A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.

Abstract: In accordance with principles of the invention, there is provided a new process for semiconductor device fabrication. The disclosed process includes forming field isolation regions on a surface of a silicon wafer, and forming gate oxide regions selectively between the field isolation regions. A gate interconnect material is deposited over the field isolation regions and gate oxide regions. A planar surface is formed on the top of the gate interconnect material. This planarization step may be accomplished by chemical mechanical polishing or some other convenient method such as a resist etch back. After planarization of the gate interconnect material, a uniform thickness photoresist is deposited on the planar surface. A gate interconnect etch pattern is formed on the planar surface using photolithography and the gate interconnect material is etched to match a gate interconnect pattern and the photoresist is removed. Sidewall spacers are provided.

Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: A semiconductor chip having a number of bonding pads on one face is mounted on a set of matching, mirror-image bonding pads on a packaging substrate, in a flip chip configuration. An alignment template is formed on and permanently secured to the substrate, and takes the form of a frame surrounding the substrate bonding pads. The height of the template is sufficient to receive the edges of the chip and hold the chip in place while the assembly is being transported to the soldering operation. No alignment operation is required, since the chip is merely placed in the receptacle formed by the template. The template is of course aligned with the substrate bonding pads when the template is created. The template can be formed on the substrate using photolithographic techniques, and, preferably, the template itself is formed of a photo-definable material.

Abstract: A method and apparatus in a computer system for updating Duplicate Tag cache status information. The invention operates in a computer system having one or more processor modules coupled to a system bus operating in accordance with a SNOOPING bus protocol. Processor commands and addresses for modification of an entry of the processor's Duplicate Tag status information is provided by the processor to its address interface to the system bus. System bus command and address information is received and stored in a interface pipeline of the address interface. A determination is made as to whether the system bus commands and addresses in the interface pipeline are valid. If there are no valid system bus commands and addresses in the interface pipeline, the Duplicate Tag status information is updated without determining if the processor commands and addresses conflict with the system bus commands and addresses.

Abstract: An apparatus and method for storing pixel data in a video memory having a plurality of slices increases the performance of line drawing by ensuring that for a given pixel, neighboring pixels in neighboring scan lines are stored in separate slices of video memory. One embodiment of the invention includes the step of appending a number of offset bits to the end of each scan line, where the number of offset bits is less than the total number of bits contained in the plurality of slices. Another embodiment of the invention rearranges the pixels of every other scan line. Another embodiment adds an offset number of pixels which is equal to the number of pixels per slice times the number of slices, then alternates ordered pixels with rearranged pixels throughout successive scan lines. Performance is further increased by providing a plurality of memory controllers corresponding to the plurality of slices of memory which may operate asynchronously to interleave memory access commands.

Abstract: A parity generator for multibit binary data in which only a subset of bits change at one time includes a circuit for determining whether the number of bits in the subset to be changed is odd or even. A toggle signal generator generates a toggle signal only if the number of bits to be changed is odd. A toggling circuit selectively changes the level of the parity bit in response to the toggle signal.

Abstract: The present invention is directed to a method for arbitrating for control of a bus in a multiprocessor system. The multiprocessor system comprises a plurality of processors and a main memory coupled to one another by the bus, each processor including a cache memory accessible by the corresponding processor and in connection with transactions on the bus. The method includes the steps of generating requests for control of the bus and granting control of the bus in respect of one of the requests. The bus is monitored for preselected transaction activity on the bus; and an idle cycle is inserted on the bus upon monitoring the preselected transaction activity.

Abstract: A computer system includes a processor having a primary cache, and a secondary cache data store, cache tag store, and memory controlled by a memory controller. The cache tag store, secondary cache data store, and memory share a common address bus. The secondary cache data store and the memory share a common data bus. In addition, some of the bits of the address bus are saved and fed directly to the memory. The memory controller provides for pipelined secondary cache accesses, during which a corresponding tag from the cache tag store is compared in the processor against the required memory address to determine if the data is located in the secondary cache. If the data is not in the secondary cache, the memory controller asserts the appropriate signals to obtain the data from memory. Because some of the address bits are fed directly to the memory, the setup time for memory control signals can be satisfied during the comparison of the cache data tag.

Abstract: The present invention is directed to a computer apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus. The bus is operated according to a SNOOPY protocol. The computer apparatus includes a processor and a cache memory coupled to the processor. The cache memory contains a subset of the data items stored in the main memory, for access by the processor and includes a TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the cache memory. A bus interface is coupled to the cache memory and is adapted for coupling to the bus. The interface operates according to the SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items of the subset having set VALID indicators and determines the identity of each initiator of a write transaction on the bus affecting a VALID data item of the subset.

Abstract: The present invention is directed to a method and apparatus for performing exchange transactions between caches and a main memory of a computer system, the caches and main memory being coupled to one another by a bus. The method includes the steps of providing caches of different sizes with a cache having a smallest size, and with each cache having an index fixed as a function of the size of the cache. For each exchange transaction, the number of bits of an index used to address a selected cache location are determined, and the upper bits of a memory address from a tag store location corresponding to the selected cache location are retrieved, where the retrieved upper address bits form an exchange address. In the event that the index of the selected cache location comprises more bits than the index of the cache having the fewest addressable locations, the excess bits of the index of the selected cache location are appended to the exchange address.

Abstract: A data storage system includes a multi-tasking processor which manages a write cache to identify adjacent blocks held in the write cache which are to be included in a next write operation, while at the same time handling data transfer requests from a system host. The processor monitors the write cache and when the cache has fewer than a predetermined number of storage locations free, initiates a block-merge task. The processor then determines which block in the write cache is least recently used and, based on virtual block numbers assigned to the data blocks, identifies the blocks in the write cache which are adjacent to the least recently used block and are within the same chunk as that block. The processor maintains a list of these adjacent blocks and the locations in which the blocks are held in the write cache.

Abstract: Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. The simulation code is preanalyzed and phase waveforms are stored each representing values occurring at a node in successive phases. Based on the preanalysis, modules are categorized in a first category, for which an event-based evaluation is to be performed in each phase of the simulation, and a second category for which no event-based evaluation need be performed in at least one but not all phases. For each phase of a second category module, an appropriate response to an event occurring with respect to the module is determined.

Abstract: An apparatus for sequencing turn-on and turn-off of power converters includes a first DC to DC converter responsive to a control signal for asserting a voltage supply signal and a sense circuit responsive to the output of said first converter to sense the level of voltage at the output of the first converter and to provide an enable signal in response to the output of said first converter when the first converter reaches a desired value. The apparatus further includes a second DC to DC converter responsive to said enable signal to provide a second supply voltage at a second different voltage level. The sequencing control has a circuit responsive to said second supply voltage and the first supply voltage, to short the second DC to DC converter to a reference potential.

Abstract: A method for providing communication between a plurality of nodes coupled in a ring arrangement, wherein a plurality of the nodes comprise processors each having a cache memory for storing a subset of shared data. Each of the nodes on the ring deposits data into a data slot during a given time period. The data deposited by each node may comprise an address field and a node field. To ensure data coherency between the caches, each processor on the ring includes a queue for saving a plurality of received data representative of the latest bus data transmitted on the bus. As each processor receives new data, the new data is compared against the plurality of saved data in the queue to determine if the address field of the new data matches the address field of any of the saved data of the queue. In the event that the new data matches one of the plurality of saved data, it is determined whether the new data represents updated data from the memory device.

Abstract: In a computer system that embodies a first hardware (X) architecture and includes a memory system and at least one simulator for a second (Y) architecture and a system for executing and debugging multiple codes having an environment manager that handles cross-domain calls, a debugging system and method are provided for debugging code in each domain as part of said multi-code executing and debugging system in a multi-architecture environment. In response to calls for debugging from either the X domain or the Y domain, commands are generated for controlling operations in both domains. User generated RUN and STEP commands control the machine execution state in the domain where debugging is performed. General support commands and debug operations support commands including EXAMINE, DEPOSIT, SET BREAKPOINT and CANCEL BREAKPOINT commands which are implemented differently for the different domains may also be user generated for controlling debugging.

Abstract: A semiconductor memory device according to the invention includes a main memory array comprising a plurality of memory sub-arrays. Each of the memory sub-arrays comprises a plurality of columns and at least one redundant column. Each column of the memory sub-array also includes multiplexing means, coupled to the input and output path of the respective column and an input and output path of a neighboring column. In addition, the redundant column is coupled to the input and output path of a neighboring column. In the event that one of the columns of the memory sub-array is defective, the multiplexing means of each of the columns between the defective column and the redundant column acts to couple the input and output paths of that column to the input and output paths of the neighboring column. With such an arrangement, the defective column is bypassed and a memory device capable of operating without defects is provided.

Abstract: A self-timed logic device which produces internal control and timing signals in response to an external signal is described. The circuit includes means responsive to a pulse signal for providing control and timing signals and means responsive to a change in state of a signal fed to said device for providing said pulse signal. The means for providing said pulse further includes means for selectively changing timing characteristics of said device in response to external tuning signals fed to the device. In a preferred embodiment the logic device is a static random access memory.

Abstract: A method for performing integrated section-level and full-chip timing verification is employed for integrated circuit designs that include several section designs. A plurality of bristle timing parameters define timing relationships between the section designs. A section-level verification procedure is performed for each of the section designs to determine whether the section designs conform to predetermined intra-section timing constraints. A full-chip verification procedure is performed for the integrated circuit design to determine the bristle timing parameters and to determine whether the integrated circuit design conforms with predetermined intersection timing constraints.