Patents Represented by Attorney, Agent or Law Firm Dicke, Billig & Czaja, P.A.
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Patent number: 7923827Abstract: Semiconductor module for a Switched-Mode Power Supply comprises at least one semiconductor power switch, a control semiconductor chip and a leadframe comprising a die pad and a plurality of leads disposed on one side of the die pad. The die pad comprises at least two mechanically isolated regions wherein the semiconductor power switch is mounted on a first region of the die pad and the control semiconductor chip is mounted on a second region of the die pad. Plastic housing material electrically isolates the first region and the second region of the die pad and electrically isolates the semiconductor power switch from the control semiconductor chip.Type: GrantFiled: July 28, 2005Date of Patent: April 12, 2011Assignee: Infineon Technologies AGInventors: Yang Hong Heng, Kean Cheong Lee, Xaver Schloegel, Gerhard Deml, Ralf Otremba, Juergen Schredl
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Patent number: 7915885Abstract: A sensing system includes a conductor with a current flow path therethrough. A first location of the conductor defines a first cross-sectional area and a second location defines a second cross-sectional area, wherein a current flowing through the conductor establishes magnetic field lines having strengths that vary according the conductor cross-sectional area. A plurality of sensors include a first and second sensors situated proximate the first and second locations, respectively, and configured to measure the magnetic field lines at their respective locations.Type: GrantFiled: August 4, 2008Date of Patent: March 29, 2011Assignee: Infineon Technologies AGInventors: Sebastian Koss, Juergen Zimmer
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Patent number: 7915089Abstract: A method and apparatus for encapsulating items such as electronic devices. A mold material is dispensed onto the electronic device and the device is situated between first and second molds. One mold is moved towards the other so as to vary the size of a cavity defined by the first and second molds. A vacuum is applied to the cavity and the vacuum is varied in response to the size of the cavity. The vacuum can be varied in response to a predetermined vacuum profile. For example, in certain embodiments the vacuum is varied in response to the position of the first mold relative to the second mold, wherein the vacuum is increased as the cavity height is reduced.Type: GrantFiled: April 10, 2007Date of Patent: March 29, 2011Assignee: Infineon Technologies AGInventors: Edward Fuergut, Irmgard Escher-Poeppel, Markus Brunnbauer
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Patent number: 7912667Abstract: An electrical test circuit is disclosed. In one embodiment, the electrical test circuit includes a first input for receiving a test signal of an integrated circuit, a second input for receiving a control signal and a third input for receiving a normalized reference signal, particularly one that is formed to be synchronous with the test signal. Using a control device of the electrical test circuit, the deviation and/or the amplitude and/or the phase of the reference signal and/or of the test signal can be varied. A measuring device generates, by subtracting the reference signal from the test signal, a difference signal which is output via an output.Type: GrantFiled: June 4, 2004Date of Patent: March 22, 2011Assignee: Infineon Technologies AGInventors: Claus Dworski, Sebastian Sattler
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Patent number: 7834609Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a first resistor, a second resistor, and a transistor. The second resistor is configured to receive a current via the first resistor. The transistor is configured to be driven via the first resistor and the second resistor and provide a compensation current. The current includes the compensation current and a reference current and changes in the current are compensated for via the compensation current which limits changes in the reference current.Type: GrantFiled: August 30, 2007Date of Patent: November 16, 2010Assignee: Infineon Technologies AGInventor: Stefan Irmscher
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Patent number: 7816229Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.Type: GrantFiled: September 30, 2008Date of Patent: October 19, 2010Assignee: Infineon Technologies Austria AGInventor: Franz Hirler
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Patent number: 7773438Abstract: An integrated circuit including an array of memory cells, volatile storage, non-volatile storage and a circuit. The circuit is configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sense first addresses. The circuit detects second defective memory cells via the sense first addresses and stores second addresses of the second defective memory cells in the volatile storage and in the non-volatile storage.Type: GrantFiled: June 6, 2008Date of Patent: August 10, 2010Assignee: Qimonda North America Corp.Inventor: Khaled Fekih-Romdhane
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Patent number: 7681063Abstract: A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.Type: GrantFiled: March 30, 2005Date of Patent: March 16, 2010Assignee: Infineon Technologies AGInventors: Hamid Partovi, Luca Ravezzi, Karthik Gopalakrishnan, Andreas Blum, Paul Lindt
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Patent number: 7659618Abstract: A semiconductor device for radio frequencies of more than 10 GHz having a semiconductor chip is disclosed. In one embodiment, the semiconductor chip, on its active top side, having a radio-frequency region and a low-frequency region and/or a region which is supplied with DC voltage. In one embodiment, the low-frequency region and/or the region which is supplied with DC voltage of the semiconductor chip is directly embedded in a plastic housing composition, the plastic housing composition is arranged such that it is spaced apart from the radio-frequency region on the active top side of the semiconductor chip.Type: GrantFiled: July 18, 2006Date of Patent: February 9, 2010Assignee: Infineon Technologies AGInventors: Jochen Dangelmaier, Klaus Pressel, Horst Theuss
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Patent number: 7655939Abstract: A nonvolatile memory cell, a memory device and a corresponding production method are disclosed. In one embodiment, a memory material region is in this case provided as memory element between a first electrode device and a second electrode device. The memory material region can be activated by means of at least one species. The memory material region is formed with or from a nanostructure.Type: GrantFiled: April 7, 2006Date of Patent: February 2, 2010Assignee: Infineon Technologies AGInventor: Klaus-Dieter Ufert
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Patent number: 7636250Abstract: A random access memory including a first amplifier, a second amplifier, a first data path, a second data path, and a first circuit. The first data path receives first data via first memory cells and the second data path receives second data via second memory cells. The first circuit is configured to receive the first data via the first data path and the second data via the second data path. The first circuit is configured to selectively provide the first data to the first amplifier and the second amplifier and the second data to the first amplifier and the second amplifier.Type: GrantFiled: July 17, 2006Date of Patent: December 22, 2009Assignee: Qimonda North America Corp.Inventors: Jiyoon Chung, Oliver Kiehl
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Patent number: 7623401Abstract: One embodiment provides a semiconductor device including a plurality of multi-bit memory cells, a first temperature budget sensor, and a circuit. Each of the plurality of multi-bit memory cells is programmable into each of more than two states. The circuit compares a first signal from the first temperature budget sensor to a first reference signal to obtain a first comparison result. The circuit refreshes the plurality of multi-bit memory cells based on the first comparison result.Type: GrantFiled: October 6, 2006Date of Patent: November 24, 2009Assignee: Qimonda North America Corp.Inventors: Jan Boris Philipp, Thomas Happ
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Patent number: 7619936Abstract: One embodiment of the present invention provides a system including a tester and a back end manufacturing system. The tester tests a resistive memory and obtains configuration data for the resistive memory. The back end manufacturing system prevents temperatures in back end processing from reducing data retention time of the configuration data in the resistive memory.Type: GrantFiled: November 16, 2006Date of Patent: November 17, 2009Assignee: Qimonda North America Corp.Inventors: Jan Boris Philipp, Thomas Happ
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Patent number: 7597235Abstract: One aspect relates to a bonding apparatus for producing a bonding connection between a bonding wire and a bonding partner. The bonding apparatus includes a heel shaper, which is provided for avoiding damage to the bonding wire in the heel region during the bonding operation. One aspect relates to a method for producing a bonding connection by means of a bonding apparatus having a heel shaper and a bonding stamp. The heel shaper is situated relative to the bonding stamp in a first active position or can be moved into such a first active position. In the first active position, the heel shaper ensures that the bonding wire runs in a permissible region in the heel region.Type: GrantFiled: November 15, 2007Date of Patent: October 6, 2009Assignee: Infineon Technologies AGInventor: Dirk Siepe
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Patent number: 7592875Abstract: An ILO circuit has a plurality of oscillator stages which are coupled to one another by means of a “tank lock” coupling. The coupling leads to an improved synchronization of the individual oscillator stages and thus to a reduced phase noise. Any desired LC oscillator topology can be used, not just the topology with PMOS and NMOS transistors. It is also possible to use SOI transistors, that is to say transistors formed on an SOI substrate. The bulk terminals of the transistors may be coupled not only to a supply voltage but, for example, also to a center potential, a reference voltage source, to ground, in floating fashion and/or to the source terminal.Type: GrantFiled: September 10, 2004Date of Patent: September 22, 2009Assignee: Infineon Technologies AGInventors: Judith Maget, Marc Tiebout
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Patent number: 7586161Abstract: One aspect of the invention relates to an edge structure for a semiconductor component having two electrodes arranged opposite one another on opposite sides of a semiconductor body having a doped zone of the first charge carrier type. The semiconductor body has at least one doped zone of the second charge carrier type extending from a surface into the depth of the semiconductor body and serving for forming a pn junction located in a central region surrounded by an edge region between the two electrodes. The edge region has at least one rectilinear edge section and at least one curved edge section and is formed in such a way that a breakdown voltage in the at least one rectilinear edge section is less than a breakdown voltage in the at least one curved edge section.Type: GrantFiled: May 23, 2006Date of Patent: September 8, 2009Assignee: Infineon Technologies AGInventor: Frank Pfirsch
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Patent number: 7582513Abstract: One aspect includes an electronic device including an integrated component with a substrate. An electrically conductive first layer region is arranged at the substrate, wherein the layer thickness of the first layer region is greater than 10 micrometers or greater than 50 micrometers.Type: GrantFiled: October 1, 2007Date of Patent: September 1, 2009Assignee: Infineon Technologies AGInventors: Werner Kroeninger, Franco Mariani
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Patent number: 7578294Abstract: An nCPAP device including a generator body defining first and second fluid flow circuits each including a tube and first and second nozzles. The tube defines a passageway forming an axial centerline. The first and second nozzles are associated with the tube and each defines an inlet and an outlet. The inlets are open to a fluid supply, whereas the outlets are open to the passageway. Each nozzle is adapted to emit a fluid jetstream from the outlet along a flow direction axis. The nozzles are arranged such that the flow direction axes are non-parallel relative to each other and relative to the axial centerline. This configuration readily induces vortex shedding during an expiratory phase, thus facilitating jet fluid flow disruption and reducing a patient's work of breathing.Type: GrantFiled: December 2, 2005Date of Patent: August 25, 2009Assignee: Allegiance CorporationInventors: Brian Pierro, Steven M. Harrington, Bruce K. Bridges, Douglas Gaylord
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Patent number: 7569903Abstract: One embodiment of the invention relates to a component arrangement including a load and an open-load detector. The load transistor has a first transistor region arranged in a semiconductor body, a second transistor region arranged in the semiconductor body and a third transistor region arranged between the first transistor region and the second transistor region and doped in complementary fashion to the first transistor region and the second transistor region. The open-load detector has a sense region arranged in the third transistor region and of conduction type complementary to the third transistor region and having an evaluation circuit connected to the sense region.Type: GrantFiled: March 7, 2006Date of Patent: August 4, 2009Assignee: Infineon Technologies Austria AGInventors: Emanuele Bodano, Nicola Macri
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Patent number: 7458588Abstract: A self-propelled vehicle comprises a frame and a platform pivotally mountable to a rear portion of the vehicle frame. The platform is pivotally movable between a first position in which the platform extends generally horizontally from the rear portion of the frame to support a rider during operation of the vehicle, and a second position in which the platform is removably secured in a generally upright position-adjacent the rear portion of the frame to enable walk-behind operation of the vehicle.Type: GrantFiled: September 8, 2005Date of Patent: December 2, 2008Inventor: Bruce E. Kallevig