Patents Represented by Attorney Donald G. Weber, Jr.

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  • Floating point processor architecture which performs subtraction with reduced number of guard bits
    Patent number: 4282582
    Abstract: There is provided a circuit and method for subtracting floating point numbers which are represented by binary bits. In this circuit, the smaller number (minuend) in one register is arranged so that the complement thereof is denormalized and added to the subtrahend (i.e. larger number) and the result of the addition is returned to the original register. At that time, the signal stored in the register is renormalized. In this circuit, the number of guard bits required to guarantee round off accuracy is only two.
    Type: Grant
    Filed: June 4, 1979
    Date of Patent: August 4, 1981
    Assignee: Sperry Rand Corporation
    Inventor: Wilson T. Wong