Abstract: An integrated circuit having a passive circuit component that can be adjusted following the manufacturing process to provide a precise absolute value for resistance or capacitance. A plurality of passive elements are selectively combinable using logic gates to include or exclude each element from a network, wherein the combined value of the included passive elements equals the value of the passive circuit component. The logic gates are set by outputs from a decoder to reduce the required inputs to the chip.

Abstract: A detector detects an exciting force externally exerted on a vibrating gyroscope by measuring a cross vibration of a regular triangular prism-shaped vibrating body having piezoelectric elements. The detector comprises an oscillator for oscillating the vibrating body at a constant frequency, a differential amplifier for differentially amplifying the piezoelectric voltages from two of the piezoelectric elements, a rectifier for rectifying an alternating current signal from the differential amplifier based on the oscillating phase of the oscillator, a direct current amplifier for amplifying a direct current signal from the rectifier, a controller for controlling output from the direct current amplifier, two operators for operating the oscillating signals from the oscillator with the signals supplied from the controller, and switches for switching on and off the output-lines of the two operators so that the piezoelectric signal supplied to the amplifier becomes a periodic linear signal.

Abstract: A switched reluctance motor having a rotor and a stator is provided the motor includes means for adjusting a relative angle between a switch turn-off angle at which a switch for supplying power to a coil is turned off, and a tooth overlap angle at which a tooth portion of the rotor and a tooth portion S of the stator are overlapped according to a predetermined calculation. The switched reluctance motor has reduced vibration and noise levels, thereby increasing their application.

Abstract: A connection matrix for a microcontroller emulation chip, which comprises memory cells of the RAM type comprising: first and second MOS transistors connected in series with each other between first and second voltage references, and having their drain terminals in common to form a first internal circuit node; third and fourth MOS transistors, also connected in series with each other between the first and second voltage references, and having their drain terminals in common to form a second internal circuit node; wherein the first and second transistors have their control terminals connected together and to the second internal circuit node, and the third and fourth transistors have their control terminals connected together and to the first internal circuit node; and fifth and sixth MOS transistors, respectively connected between first and second input terminals of the RAM cell and the first and second internal circuit nodes, and having respective control terminals connected to a third input terminal of the RA

Abstract: The reading circuit comprises a current source, which, via a current reflection circuit, supplies a constant predetermined current to a cell to be read, an operational amplifier with a non-inverting input connected to the drain terminal of the cell, and an output connected to the gate terminal of the cell. The source terminal of the cell is connected to ground. Thereby the output voltage of the operational amplifier supplies directly (at the set current) the threshold voltage of the cell, and the drain terminal of the cell is biased to a positive voltage.

Abstract: An analog-signal to square-wave-signal reshaping system for threshold-dependent reshaping of an analog input signal to a square wave signal; comprising an offset-inflicted reshaping circuit having a signal input adapted to be fed with the analog input signal, a reference input adapted to be fed with a reference voltage determining the reshaping threshold, and a signal output from which the square wave signal is available; an offset storage circuit connected to the signal input of the reshaping circuit and adapted to store a charging voltage corresponding to the offset voltage of the reshaping circuit, with this charging voltage being adapted to be superimposed on the analog input signal for offset compensation; a controllable switch circuit which in a first switching state takes no influence on the reshaping function of the reshaping circuit and, for the purpose of offset compensation, in a second switching state interrupts the reshaping operation of reshaping circuit and effects charging of the offset storag

Abstract: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Abstract: A level shift circuit for a voltage input signal (S, SN) presenting at least a first and a second high-voltage levels, the circuit comprising two parallel branches, each formed by a current modulator and a signal converter. The current modulators are supplied with two signals in phase opposition to each other, and generate current signals whose value depends on the level of the respective input signal; and the signal converters convert the current signals into ground-related voltage signals. The signal converters together form a single-ended differential circuit, the output of which therefore presents a low-voltage digital signal which can be processed by normal digital circuits and is unaffected by noise or variations in supply voltage.

Abstract: An electric circuit having a switchable feedback branch switchable between a first feedback state, in which the circuit arrangement has a frequency response that is stable with respect to an oscillation tendency, and a second feedback state, in which the circuit arrangement has a frequency response that is unstable with respect to an oscillation tendency. The circuit includes a switchable frequency response compensation circuit which during the first feedback state of the feedback branch can be controlled to an ineffective state and during the second feedback state of the feedback branch can be controlled to an effective state, and in the effective state causes such compensation of the frequency response of the circuit arrangement in the second feedback state that the circuit arrangement in the second feedback state remains stable with respect to an oscillation tendency.

Abstract: An analog reading circuit having a current mirror circuit forcing two identical currents into a cell to be read and into a reference cell. An operational amplifier has an inverting input connected to the drain terminal of the cell to be read, a non-inverting input connected to the drain terminal of the reference cell, and an output connected to the gate terminal of the reference cell. The reference cell therefore forms part of a negative feedback loop which maintains the overdrive voltages of the cell to be read and the reference cell constant, irrespective of temperature variations. The reading circuit is also of high precision and has a high reading speed.

Abstract: This invention relates to a voltage comparator with an input for an analog signal and an output for a digital signal, comprising an inverter which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors coupled to each other, at least one of the two MOS transistors being of the floating gate type.

Abstract: An electrically erasable and programmable non-volatile memory device comprises at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and activating respective redundancy columns when the defective columns are addressed.

Abstract: In a first operation mode the level shifter transmits as output a logic input signal and in a second operation mode it shifts the high logic level of the input signal from a low to a high voltage. The level shifter comprises a CMOS switch and a pull-up transistor; the CMOS switch comprises an NMOS transistor and a PMOS transistor which are connected in parallel between the input and the output of the shifter and have respective control terminals connected to a first supply line at low voltage and, respectively, to a control line connected to ground in the first operation mode and to the high voltage in the second operation mode; the pull-up transistor is connected between the output of the shifter and a second supply line switchable between the low voltage and the high voltage and has a control terminal connected to the first supply line.

Abstract: The circuit is for translating a switching signal disposed between ground level and Vdd to a translated switching signal disposed between first and second voltages Vhsrc and Vhstrap. The circuit includes a bistable circuit formed by two branches which include two nMOS transistors the sources of which are connected to ground and are controlled, respectively, by a switching-on signal and by a switching-off signal derived from the switching signal by means of a buffer and an inverter, respectively. Two pMOS transistors having their sources at the voltage Vhstrap and the drain of one connected to the gate of the other output the translated switching signal at one of their drains. Two further pMOS transistors having gates at the first voltage Vhsrc are interposed between the two nMOS transistors and the two pMOS transistors.

Abstract: A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

Abstract: A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.

Abstract: A circuit for driving a bridge circuit BR having a signal input I1,I2, and a signal output O1-O2, and at least two conduction control signals C1 and C2 by the PWM procedure. The circuit includes a first virtually-square-wave generator CO1 having an output coupled to one of the two control inputs and a second virtually-square-wave generator CO2 having an output coupled to the other of the two control inputs. In this manner, the bridge is driven by two square waves, the null value of the current at the output )O1-O2 no longer constitutes an intrinsic discontinuity and any value, even around zero, is controllable with relative ease.

Abstract: An electric circuit comprising at least one MOS switching transistor disposed on the side of high potential and a switchable charge pump supporting the switching-on phase of the MOS switching transistor at a pumping voltage output thereof with a pumping voltage higher than the potential of the supply voltage on the side of high potential at a pumping voltage output thereof. A control gate of the MOS switching transistor is connectable by means of a controllable switch to a high-potential-side supply voltage terminal or to the pumping voltage output depending on whether a predetermined threshold value on the switching-on ascending edge of the MOS switching transistor signal is exceeded or not.

Abstract: The memory device has a plurality of local boost circuits, each connected to a sector of the memory array, and each having a control circuit, at least a respective boost capacitor, and a respective drive circuit. Each drive circuit is only enabled in read mode, on receiving an address-transition-detect signal and a sector enabling signal, for reading memory cells forming part of the respective sector. The boost voltage is only supplied to the final inverter of the row decoder. A clamping diode limits the boost voltage to prevent undesired direct biasing of the PMOS transistors of the final inverters connected to the nonaddressed word lines. And the overvoltage is therefore only supplied locally when and where necessary.