Patents Represented by Attorney, Agent or Law Firm Edward C. Kwok, Esq.
  • Patent number: 6542116
    Abstract: To determine the clock doppler of a signal receiver, sampled data received from a receiver into are divided into data segments of incremental length. The clock doppler is estimated based on correlating each data segment with the expected signal from each satellite, from a set of satellites, that is overhead the receiver. For each data segment, the correlated result of each satellite is used to refine subsequent calculations of the clock doppler of the next overhead satellite. When the clock doppler calculations for a data segment have been performed using all overhead satellites from the set of satellites, then the results for that data segment are used to refine the calculations for the next data segment.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: April 1, 2003
    Assignee: Enuvis, Inc.
    Inventors: Anant Sahai, Andrew Chou, Wallace Mann, Stefano Casadei
  • Patent number: 6535163
    Abstract: To determine the location of a signal receiver, sampled data received from a receiver is divided into data segments of increasing length. Current ranges for a delay value and for a modulation frequency value are calculated relative to each satellite signal source that is overhead the signal receiver. Using the data segments of increasing length, the current ranges, estimates for the delay value and for the modulation frequency value are then iteratively calculated and updated. For each signal source, I and Q correlation integrals and their magnitude values are calculated using the modulation frequency value estimate and each of a range of delay values centered around the delay value estimate. The resulting magnitude-curve is interpolated using the calculated magnitude values. The location of the receiver is calculated using the shape of the magnitude-curve to represent the I and Q correlation integrals for each signal source.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: March 18, 2003
    Assignee: Enuvis, Inc.
    Inventors: Anant Sahai, John Tsitsiklis, Benjamin Van Roy, Andrew Chou, Wallace Mann, Jesse Robert Stone, Wungkum Fong
  • Patent number: 6525688
    Abstract: Some embodiments of the invention provide a location-determination system that includes several transmitters and at least one receiver. Each transmitter transmits a signal that includes a unique periodically-repeating component, and the receiver receives a reference signal. Based on the received reference signal, the location-determination system identifies an estimated location of the receiver as follows. For each transmitter in a set of transmitters, the system computes a phase offset between the received reference signal and a replica of the transmitter's periodically-repeating component. The system also identifies an approximate location of the receiver and an approximate receive time for the received signal. The system then uses the identified approximate location and time, and the computed phase offsets, to compute pseudoranges for the set of transmitters. Finally, the system identifies the estimated location of the receiver by using the computed pseudoranges.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: February 25, 2003
    Assignee: Enuvis, Inc.
    Inventors: Andrew Chou, Benjamin Van Roy, John Tsitsiklis
  • Patent number: 6525687
    Abstract: Some embodiments of the invention provide a location-determination system that includes a number of transmitters and at least one receiver. Based on a reference signal received by the receiver, this location-determination system identifies an estimated location of the receiver within a region. In some embodiments, the system selects one or more locations within the region. For each particular selected location, the system calculates a metric value that quantifies the similarity between the received signal and the signal that the receiver could expect to receive at the particular location, in the absence or presence of interference. Based on the calculated metric value or values, the system identifies the estimated location of the receiver.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: February 25, 2003
    Assignee: Enuvis, Inc.
    Inventors: Benjamin Van Roy, John Tsitsiklis, Andrew Chou
  • Patent number: 6372614
    Abstract: A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.
    Type: Grant
    Filed: May 19, 2001
    Date of Patent: April 16, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bharath Rangarajan, Ramkumar Subramanian, Bhanwar Singh
  • Patent number: 6365924
    Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: April 2, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Albert Z. H. Wang, Chen H. Tsay, Peter Deane
  • Patent number: 6362061
    Abstract: A method of manufacturing devices with source, drain and extension regions is provided. To achieve in the extensions a depth and dopant levels different from the source and drain regions, a channel-shaped oxide structure is formed surrounding a polysilicon gate. The channel-shaped oxide structures forms an implantation barrier over the extensions region. Thus, when the source and drain implantation is carried out at a given energy, the extension regions receives a 35-40 percent dopant dose, as compared to the dose received by the source region and the drain region.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: March 26, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Sunny Cherian
  • Patent number: 6356107
    Abstract: An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: March 12, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: Howard Y. M. Tang, Albert Chan, Cyrus Y. Tsui, Ju Shen
  • Patent number: 6348701
    Abstract: The concentration of metal atoms in a field area between two trench structures is determined by applying a voltage on one of the trench structures and grounding the other. The resultant current flow between the trench structures is measured and used as an indicator of metal concentration in the field area.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: February 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Young-Chang Joo, Amit P. Marathe
  • Patent number: 6304099
    Abstract: An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: October 16, 2001
    Assignee: Lattice Semiconductor Corporation
    Inventors: Howard Y. M. Tang, Albert Chan, Cyrus Y. Tsui, Ju Shen
  • Patent number: 6296709
    Abstract: An improved vertical diffusion furnace for semiconductor manufacturing processes is provided. Temperature and flow rate management enables more uniform temperature distribution across the wafer during ramp up and ramp down, thereby preventing wafer warp.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: October 2, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Patent number: 6291254
    Abstract: A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: September 18, 2001
    Assignee: Sequence Design, Inc.
    Inventors: Shih-tsun Alexander Chou, Keh-Jeng Chang, Robert G. Mathews
  • Patent number: 6292185
    Abstract: A method and apparatus for tailoring the appearance of a graphical user interface, specifically an internet web browser. A host server receives a request over the internet or an intranet for a web page. The host server provides the necessary data and executable files for the user's personal computer. A computer program executed on a personal computer alters the appearance of a user's graphical web browser by accessing data files. The appearance of a web browser can be tailored using an editor program to provide data files used to tailor the appearance of a web browser.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: September 18, 2001
    Assignee: C.C.R., Inc.
    Inventors: Bong Su Ko, Jae Hyun Kim, Seok Ho Youn
  • Patent number: 6284608
    Abstract: A method of manufacturing an accumulation mode n-channel Silicon On Insulator (SOI) transistor includes forming an intrinsic silicon body region implanted with two deep Boron and one shallow Phosphorous implants; forming source/drain regions each implanted with Arsenic; and forming p-type regions adjacent each of the source and drain regions and disposed along the transistor channel. The SOI transistor has a higher transconductance than known SOI devices.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: September 4, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivakapic, Srinath Krishnan, Witold Maszara
  • Patent number: 6281078
    Abstract: Polystringers that cause NAND-type memory core cells to malfunction are covered by ONO fence material. ONO fence is removed so that polystringers may then be removed more readily. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. The device is next exposed to an hydrogen-fluoride solution to remove oxide-based materials, particularly ONO fence. Thereafter, the polystringers are exposed and may thus be removed more readily.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: August 28, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kent Kuohua Chang, Yuesong He, John Jianshi Wang, Ken Au
  • Patent number: 6271591
    Abstract: A method for fabricating copper-aluminum metallization utilizing the technique of electroless copper deposition is described. The method provides a self-encapsulated copper-aluminum metallization structure.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: August 7, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Valery Dubin, Chiu Ting
  • Patent number: 6266099
    Abstract: A video pre-amplifier includes an input stage and an output stage. In one embodiment, an on-screen display signal is provided to the output stage, and a control signal is asserted when the on-screen display signal is active. With respect to a video output signal, both the gains of the input stage and output stage are adjusted when the control signal is asserted. In one embodiment, the control signal is generated by a comparator within the output stage.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: July 24, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Tuong Hai Hoang
  • Patent number: 6265248
    Abstract: In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: July 24, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Johan Darmawan, Christian Olgaard, Tsung Wen Lee
  • Patent number: 6266803
    Abstract: A method for routing clock signals in an integrated circuit provides a hierarchical routing scheme in which the lowest level clock buffers are first placed row by row in preallocated locations and routed to the input pins of standard cells receiving the output clock signals of these clock buffers. Under the method, the number of clock buffers to be placed in each row is computed according to estimates of their load capacitances and expected wiring lengths within a window. The output buffers of the same clock signal are gridded or strapped together to minimize clock skew. A second level of clock buffers are then assigned to drive the lowest level buffers. The hierarchy can be extended to any number of higher levels, until clock signals are routed for the entire integrated circuit. The higher level clock signals can also be strapped or gridded to minimize clock skew.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: July 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alisa M. Scherer, Frederick Weber
  • Patent number: 6263390
    Abstract: The present invention provides a two-port memory to connect a microprocessor bus to multiple peripherals. In one embodiment, an apparatus for an IO gateway subsystem of a microprocessor includes a bus of the microprocessor connected to a two-port memory, and a first peripheral connected to the two-port memory and a second peripheral connected to the two-port memory. In particular, the two-port memory communicates with the bus at a first clock rate, the two-port memory communicates with the first peripheral at a second clock rate, and the two-port memory communicates with the second peripheral at a third clock rate, in which the first clock rate, the second clock rate, and the third clock rate are asynchronous (e.g., the clocks have different phases, or the clocks have different frequencies).
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: July 17, 2001
    Assignee: ATI International SRL
    Inventors: Ali Alasti, Govind V. Malalur