Abstract: Systems and methods of addressing two or more banks of memory utilizing a single-bank serial peripheral interface and an at least three-byte address protocol are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to address one of the memory banks using the three-byte addressing scheme, and to write data to or read data from the addressed bank, and a bank register pointer component coupled to the serial processing component, the pointer component comprising two or more bank register pointers associated with respective memory banks, and configured to select one of the memory banks based on the two or more bank register pointers, wherein the bank register pointer component selects one of the two or more memory banks, and the serial processing component writes data to or reads data from the selected bank of memory according to the three-byte addressing scheme.

Abstract: An ion implantation system comprising an ion source configured to generate an ion beam along a beam path, a mass analyzer is located downstream of the ion source wherein the mass analyzer is configured to perform mass analysis of the ion beam and a beam complementary aperture located downstream of the mass analyzer and along the beam path, the beam complementary aperture having a size and shape corresponding to a cross-sectional beam envelope of the ion beam.

Abstract: Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.

Abstract: The invention relates to a gas-diffusion electrode for chlor-alkali electrolysis cells integrated in a percolator of plastic porous material suitable for being vertically crossed by a downward flow of electrolyte. The electrode comprises a catalytic composition based on silver and/or nickel mixed to a polymeric binder, directly supported on the percolator without any interposed reticulated metal current collector.

Abstract: One embodiment of the present invention relates to a network element that is configured to be associated with a network having a number of nodes. The master node is configured to communicate with a number of nodes and allocate bandwith therebetween by sending outgoing signals and receiving incoming signals over a transmission medium. The master node is further configured to adaptively account for hidden nodes with which the master node cannot bi-directionally directly communicate by communicating at least one signal with at least one proxy node. Other methods and network elements are disclosed.

Abstract: The present invention involves a beam energy identification system, comprising an accelerated ion beam, wherein the accelerated ion beam is scanned in a fast scan axis within a beam scanner, wherein the beam scanner is utilized to deflect the accelerated ion beam into narrow faraday cups downstream of the scanner, wherein a difference in scanner voltage or current to position the beam into the Faraday cups is utilized to calculated the energy of ion beam.

Abstract: A power control system includes a reference path filter used to suppress high frequencies in an input signal and generate a filtered envelope signal, a reference path amplifier to scale the filtered input signal based on a gain signal and generate a reference signal, a signal path amplifier to amplify an RF modulated signal and generate a signal path output signal scaled by a gain of an actuator signal, and a power detector to detect a power associated with the signal path output signal. The system includes an ADC to receive, pre-filter and convert the detected envelope signal into a measurement signal, and a comparator block to receive the reference signal and the measurement signal, and generate an error signal based on the difference, and a controller to generate the actuator signal for controlling the gain of the signal path amplifier based on the error signal.

Abstract: In a buffer (10) to compensate for runtime fluctuations of data packets (1) transmitted over a transmission line (40), in order to be able to set optimally an additional retransmission delay by the buffer (10) it is proposed to calculate the probable hold time of a data packet (1) immediately after arrival of a data packet (1) in the buffer (10). The additional retransmission delay by the buffer (10) is set based on the probable hold time of the data packets (1) in the buffer (10). To guarantee optimum setting of the retransmission delay, both the maximum detected probable hold time and the minimum detected probable hold time of the data packets (1) are used. This is achieved preferably by means of a minimum value detector and a maximum value detector which detect extreme values of the probable hold time occurring at specific time intervals.

Abstract: The interference suppression processing unit includes Na?1 receiver paths to transmit respective Na?1 received data sequences received from respective Na?1 antennas, and a signal generation unit to generate K?Na signal data sequences from the received data sequences. The interference suppression processing unit also includes K?Na signal paths that each transmit one of the signal data sequences, a prefilter unit in each one of the signal paths, and a combiner having K?Na input terminals each one connected to an output terminal of one of the prefilter units.

Abstract: A discrete sampling control signal, which influences the sampling time, from a sampling phase selection element is calibrated by definition of quantization intervals for a sampling time error signal. For this purpose, a received signal is shifted through a series of time shifts ?i in the signal path upstream of the sampling phase selection element. The sampling time errors ei associated with the respective time shifts ?i are measured. The quantization steps of the sampling control signal that are suitable for the sampling phase selection element are then determined from the relationship obtained between ?i and ei.

Abstract: A tire pressure measurement system (TPMS) includes a capacitor and an integrated circuit configured to receive a supply voltage. The integrated circuit includes a voltage regulator and a measurement unit. The voltage regulator is configured to be turned on and off for predetermined periods of time such that the capacitor is charged and discharged, respectively. The voltage regulator and the capacitor are connected to the measurement unit in order to selectively provide electric charge at a voltage between predetermined upper and lower limits.

Abstract: A photovoltaic inverter with an inverter housing includes at least a first chamber and a second chamber separated by a wall. The first chamber has a higher Ingress Protection (IP) rating than the second chamber. The first chamber accommodates at least one electronic component part of the photovoltaic inverter. A surface of the wall facing the second chamber provides a plurality of fuse housings. Each of the fuse housings accommodates a fuse and being coupled to a plug connector electrically connected to the fuse. The plug connectors provide electrical connections to the first chamber.

Abstract: An inverter (1) for feeding electric power into a utility grid (7) or into a load is described. The inverter (1) contains two direct voltage inputs (2, 3), one first intermediate circuit (8) connected thereto and comprising two series connected capacitors (C1, C2) that are connected together at a ground terminal (14), two alternating voltage outputs (5, 6) of which one at least is provided with a grid choke (L1) and one bridge section (10). In accordance with the invention, a second intermediate circuit (9) that is devised at least for selectively boosting the direct voltage and is intended for supplying the bridge section (10) with positive and negative voltage is interposed between the first intermediate circuit (8) and the bridge section (10).

Abstract: The present invention facilitates overall system performance by balancing system resource utilization and network throughput. The invention analyzes packets received from host software selects one or more of buffers to coalesce into a single, coalesced buffer. The selection is based upon an initial fragment size selected to facilitate overall system performance. The coalesced buffer and non-coalesced buffers, are passed to a network device for transmission.

Abstract: A sensor has a suspended mechanical resonator being responsive to one of a linear acceleration and an angular velocity of the sensor such that a first area and a second area are subjected to opposite elongation movements and responsive to the other such that the first area and the second area are subjected to a common elongation movement, a first mechanical-electrical interface interacting with the first area, a second mechanical-electrical interface interacting with the second area, a common mode signal generator coupled to the mechanical-electrical interfaces with a common mode signal output, a differential mode signal generator coupled to the mechanical-electrical interfaces with a differential mode signal output, a first processing circuit coupled to the differential mode output, with an output for a first processed signal, and a second processing circuit coupled to the common mode output with an output for a second processed signal.

Abstract: An electrostatic chuck and method for clamping and de-clamping a workpiece is provided. The ESC comprises a clamping plate having a clamping surface, and one or more electrodes. An electric potential applied to the one or more electrodes selectively clamps the workpiece to the clamping surface. An arc pin operably coupled to the clamping plate and a power source provides an arc for penetrating an insulating layer of the workpiece. The arc pin is selectively connected to an electrical ground, wherein upon removal of the insulative layer of the workpiece, the arc pin provides an electrical ground connection to the workpiece.

Abstract: One embodiment relates to a network. The network includes a first splitter having an input port and N output ports. A first network node is associated with a first of the N output ports. A second network node is associated with a second of the N output ports and is adapted to receive signals communicated from the first network node through the first splitter. Other apparatuses and methods are also set forth.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: An ion source includes a first plasma chamber including a plasma generating component and a first gas inlet for receiving a first gas such that said plasma generating component and said first gas interact to generate a first plasma within said first plasma chamber, wherein said first plasma chamber further defines an aperture for extracting electrons from said first plasma, and a second plasma chamber including a second gas inlet for receiving a second gas, wherein said second plasma chamber further defines an aperture in substantial alignment with the aperture of said first plasma chamber, for receiving electrons extracted therefrom, such that the electrons and the second gas interact to generate a second plasma within said second plasma chamber, said second plasma chamber further defining an extraction aperture for extracting ions from said second plasma.

Abstract: The present invention relates to a flash memory array. The flash memory array includes at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further includes a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level.