Abstract: An Ethernet switch has at least one ingress/egress port 1 which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces 3 each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules 5, 7 which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces. If there are 8 such ports in the Ethernet switch, then by switching different numbers of the ports between the two modes, the switch may operate in 9 different modes: as 8 GE ports, 7 GE ports and 8 FE ports, 2 GE ports and 48 FE ports, 1 GE port and 56 FE ports, or simply as 64 FE ports.

Abstract: In a method for channel qualification and selection, an actual data packet length and a data packet error rate in a received data packet are determined, and are used for a qualification decision. The measured data packet error rate is compared with a previously calculated data packet error threshold value, which depends on an assumed bit error rate and the ratio of a possible actual to a maximum data packet length.

Abstract: A tire tread sensing system includes a magnetic field sensor and a magnetic field source configured to magnetize magnetizable particles embedded in a tire tread. The magnetic field sensor is configured to measure a magnetic field strength associated with the magnetic field source and the magnetizable particles, and the magnetic field strength is indicative of a tire tread depth. Alternatively, the particles comprise alternating permanent magnets embedded in a tread portion of a tire.

Abstract: In a method for producing bases with external contacts for surface mounting on circuit mounts, bases with external contacts are electrodeposited on semiconductor wafers or semiconductor chips. Subsequently, electrodeposited bases with external contacts are heat treated on the semiconductor wafers or the semiconductor chips at temperatures below the melting temperature of the deposited contact base material. Thereafter, a so-called RTP process is carried out in the form of a high-temperature interval in which the melting temperature is reached. Subsequently, the surfaces of the bases with external contacts are wet etched, the overall method being terminated by a cooling and drying operation. The bases with external contacts thus produced can be reliably surface mounted on circuit mounts.

Abstract: The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate charge-loss by providing protection against charging up of the various lines as a result of further plasma etching processes. The salicide block equalizes the charge dissipation in the memory array by providing each wordline path with a varied amount of resistance in addition to the total path resistance. Because the charge protection provided to each wordline otherwise varies depending on the resistance path to a common discharge element, a salicide block for resistance equalization provides greater reliability and predictability during processing. Other such shapes conducive for any desired resistance path fall within the scope of the invention.

Abstract: A device and a method for transmitting a MAC service data unit (MSDU) in a network system are disclosed. The MSDU has a plurality of pieces of frame data. The method includes receiving the pieces of frame data of the MSDU; and when finishing receiving each piece of frame data, even if not all of the pieces of frame data of the MSDU have been received, converting the received piece of frame data into a MAC protocol data unit (MPDU) and outputting the MPDU.

Abstract: A method for equalization of a signal is provided, wherein the equalization is of a signal that is transmitted via a data channel based on the DF method. The method takes account of at least one interference channel, and includes processing of at least two trellis diagrams in each time unit, with the states of at least one of the trellis diagrams describing the data channel. A DF contribution that is used for processing of this trellis diagram includes information about at least one interference channel.

Abstract: A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present invention can be substantially the same as the minimum feature size, even at very small minimum feature size.

Abstract: A polar modulator contains a phase locked loop which is designed to emit a radio-frequency signal at one frequency to one output, with the frequency being derived from the reference signal and from a phase modulation signal at a control input of the phase locked loop. The modulator additionally has a second signal input for supplying an amplitude modulation signal. The second signal input is connected to a control input of a pulse width modulator, one of whose signal inputs is coupled to the output of the phase locked loop. The pulse width modulator is designed to vary the duty ratio of a signal which is applied to the signal input, with this variation being adjustable via a regulation signal at the control input. A filter can be connected downstream from the output of the pulse width modulator and suppresses higher harmonic components in a signal which can be tapped off at the output of the pulse width modulator.

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip being punctually attached to said substrate on said first surface of said substrate via a single attachment point; and means for protecting said semiconductor chip on said first surface of said substrate at least protecting said semiconductor chip laterally.

Abstract: A circuit arrangement for regulating a parameter (e.g., duty cycle) of an electrical signal, generated by a circuit component. The regulating device includes a first integrator, which is supplied with the output signal from the circuit component, and a second integrator, which is supplied with the output signal from the first integrator. The second integrator has an operational amplifier having an inverting input, a noninverting input and an output, and the output is fed back to the inverting input via a feedback path. The inverting input receives the output signal from the first integrator. The noninverting input receives a reference signal. The output of the operational amplifier is fed back to the inverting input via a series circuit including a capacitor and a resistor. The output of the second operational amplifier provides an output signal from the regulating device, which is supplied to the circuit component as a controlled variable.

Abstract: The invention relates to an electrical arrangement having a mount device with at least one conductor track, having an electrical component that is mounted on the mount device and is electrically connected to the at least one conductor track. The arrangement further includes a housing base plate on which the mount device is mounted and through which at least one contact-making pin extends, with the at least one contact-making pin being electrically connected to the at least one conductor track. In order to improve the frequency response of the arrangement, the invention provides for the at least one contact-making pin to touch the mount device and, in the area of the touching point, for a connection without any bonding wire to be provided between the at least one contact-making pin and the at least one conductor track on the mount device.

Abstract: A memory cell that includes a substrate that has a first region and a second region with a channel therebetween. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge, wherein the first region is doped to such an extent that electric fields are reduced at the locations in the substrate where impact ionization occurs during programming.