Abstract: An interpolator and method for high image resolution by interpolation with adaptive filtering of Bayer pattern color signals, and a digital image signal processor implementing the same. The digital image signal processor can generate interpolation data close to actual pixel data by applying a nonlinear low pass filter (LPF) that reflects the change rate of the data centered around a center pixel and the data of the center pixel, and by simultaneously applying a LPF, a band pass filter (BPF), and a high pass filter (HPF) having linear characteristics, and can generate interpolation data that reduces aliasing (at “edges”) and emphasizes a high frequency component.

Abstract: An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage.

Abstract: A clock multiplier for multiplying an input clock by N includes a phase/frequency detector, a clock selector, and a voltage-controlled delay line. The phase/frequency detector generates a first control signal and a second control signal according to a frequency/phase difference between the input clock and a count signal indicating a signal that is generated by delaying the input clock N times. The clock selector selects one of the input clock and a feedback clock based on the input clock and the count signal. The voltage-controlled delay line adjusts a delay time of the selected signal according to a control voltage that is generated based on the first control signal and the second control signal, and outputs the feedback clock based on the adjusted signal. The clock multiplier operates without accumulating a frequency/phase difference between the input clock and the output clock when the multiplying ratio is increased.

Abstract: A stencil mask includes a membrane forming thin layer having membrane areas and a border area that limits the membrane areas. The membrane areas have a plurality of pattern areas which include an aperture through which particle beams can permeate and non-pattern areas interposed between the pattern areas. A main strut supports the membrane areas and is formed on the border area of the membrane forming thin layer. An auxiliary strut is formed in the non-pattern areas inside the membrane pattern area such that the auxiliary strut divides the membrane areas into plural divided membrane areas. The auxiliary strut supports the divided membrane areas.

Abstract: A channel equalizer obtains channel impulse responses (CIRs) for all subcarriers by way of filtering channel impulse responses of specific subcarriers using at least two filters. One of the two filters may be a low pass filter. At least one other of the at least two filters is implemented as a band pass filter having a variable filtering bandwidth, being available to establish various filtering bandwidths in response to various multi-path channel environments. By improving the performance of channel estimation, equalization may be improved.

Abstract: A feedback-type variable gain amplifier including a first field effect transistor, a feedback circuit, and a load circuit. The first field effect transistor receives an input voltage signal through an input node, amplifies the input voltage signal, and outputs the amplified input voltage signal through an output node. The feedback circuit is coupled between the input node and the output node, and generates feedback impedance that is changed in response to a control signal. The load circuit is coupled between the output node and a voltage source, and generates load impedance that is changed in response to the control signal to cancel a change of input impedance due to a change of the feedback impedance. Therefore, since the input impedance is not changed when the gain of the amplifier is changed, a voltage standing wave ratio is good, and a range of gain control is broad.

Abstract: A voltage-controlled oscillator (VCO) for a multi-band receiver, and a radio-frequency (RF) communication apparatus having the same. The VCO includes at least two fine tune branches, that is, a main fine tune branch and an auxiliary fine tune branch. The main fine tune branch includes at least one variable capacitor whose capacitance varies according to a tuning voltage. The auxiliary fine tune branch includes at least one varactor that operates either as a variable capacitor whose capacitance varies according to the tuning voltage or a fixed capacitor regardless of the tuning voltage, based on an operating frequency band. Accordingly, it is possible to prevent phase noise from increasing by varying the gain of the VCO according to the frequency band of an oscillation signal from the VCO.

Abstract: Provided are a CMOS image sensor (CIS) type image sensing device for averaging and sub-sampling analog image signals at a variable sub-sampling rate and a method of driving the same. The image sensing device includes: a two-dimensional active pixel sensor (APS) array including pixels arranged in rows and columns; an averaging unit averages reset signals and image signals alternately generated from each of pixels corresponding to odd- numbered and even-numbered rows and columns in based on a predetermined sub-sampling rate in a sub-sampling mode by repeating a method of accumulating, averaging, (and dumping) the reset signals and the image signals, and generating a comparison signal corresponding to a difference between the average of the reset signals and the average of the image signals; and a conventional digital signal output circuit that generates digital signals corresponding to the sub-sampled (averaged) image signals generated from the pixels represented by the comparison signal.

Abstract: In a liquid crystal display apparatus, a lower substrate has a transmissive electrode formed in a transmissive area of a first substrate and a reflective electrode formed in a reflective area of the first substrate. An upper substrate has a second substrate, a first insulating layer formed on the second substrate corresponding to the transmissive area, a common electrode formed on the first insulating layer and the second substrate corresponding to the reflective area, and a second insulating layer formed on the common electrode corresponding to the reflective area. Accordingly, the liquid crystal display apparatus may have a uniform cell gap, thereby improving a reflectance and a transmittance thereof.

Abstract: A source driving circuit includes a shift register, a data latch circuit, a D/A converter, and a sample-and-hold circuit. The shift register generates an n-bit first signal in response to a clock signal and an input/output control signal, wherein n is a positive integer. The data latch circuit samples video data using the first signal to latch the sampled video data, and outputs 3×n digital signals. The D/A converter generates a plurality of analog voltage signals corresponding to the 3×n digital signals using a plurality of gray scale voltages. The sample-and-hold circuit generates 6×n sample-and-hold signals using the analog voltage signals in response to a plurality of switching control signals.

Abstract: A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in one of the first and second operation modes; and a memory control unit for storing area information discriminating between the first memory area and the second memory area and generating memory control signals for controlling access to the first memory area and the second memory area. One memory can be substituted for a memory combination including ROMs and RAMs in one chip.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor and a method for operating the same are provided. The CMOS image sensor includes a pixel array unit having a matrix of pixels, wherein each pixel comprises a charge transfer element for transferring charge collected in a photoelectric conversion element to a charge detection element, and a row drive unit for supplying a voltage to the charge transfer element during part of a charge integration period of the photoelectric conversion element, wherein the supplied voltage causes the charge transfer element to have a negative potential.

Abstract: In an LCD for enhancing a reflection ratio, a second substrate faces the first substrate on which a pixel array is formed, a liquid crystal layer is interposed between the first and second substrates, an insulating layer on the first substrate includes first regions and second regions, where each of the second regions has a height difference relative to each of first regions, a base line of a first region forms an angle from about 5 to about 15 degrees with respect to a tangent line of a second region, an embossing pattern with a uniform and low stepped portion is formed by regulating an exposure amount applied to the organic insulating layer so that a reflection ratio is maximized and a distribution of the slopes of an embossing pattern is uniform, and the reflection ratio is enhanced in a specific direction by forming the embossing pattern with an asymmetric profile.

Abstract: A digital/analog converting driver and a digital/analog converting method, in which the digital/analog converting driver converts digital data having M+N (M and N are integers) bits into an analog voltage and includes a first converting unit, a second converting unit, and an analog voltage outputting unit. The first converting unit converts successive M bits of the digital data into a first voltage. The second converting unit converts successive N bits of the digital data into a second voltage. The analog voltage outputting unit adds the first voltage and the second voltage and outputs the added voltage as the analog voltage. The output range of the first voltage is different from that of the second voltage.

Abstract: A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.

Abstract: A semiconductor memory device controlling an output voltage level of a high voltage generator in response to a variation of temperature has a high voltage generator that provides a high voltage higher than a power source voltage through an output terminal, generates a temperature detection signal obtained by sensing a variation of a diode current based on a temperature variation, and adjusts a voltage level of the output terminal in response to the temperature detection signal. The device is able to automatically control an output voltage or current of the high voltage generator.

Abstract: A TFT array panel on which both pixel electrodes and common electrodes are formed and a color filter panel is disposed opposing the array panel, and liquid crystals are interposed therebetween. The liquid crystals are aligned parallel to the two panels and driven by parallel electric field formed between the pixel electrodes and reference electrodes. Polarization films are arranged outsides the two panels, and a quasi-A plate compensation film is arranged between the color filter panel and the polarization film.

Abstract: A lamp socket that supports a lamp including a lamp body and one or more electrodes protruding from opposite end portions of the lamp body and that electrically connects an inverter circuit board driving the lamp and the lamp includes: a socket terminal having a first stopper where the electrodes are inserted in a first direction crossing a lengthwise direction of the electrodes to be held, the socket terminal providing an elastic force in a second direction substantially crossing the lengthwise direction of the electrodes and the first direction, whereby the first stopper is closely held to the electrodes.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor and a method of driving the CMOS image sensor that can reduce the number of devices required by each of a plurality of pixels and can stably drive the pixels, in which each of the pixels includes a photodiode that converts light energy into an electrical signal, a transfer transistor that transmits photocarriers stored in the photodiode to a floating diffusing region, a drive transistor that has a gate connected to the floating diffusion region and drives a voltage signal according to a voltage of the floating diffusion region, the voltage signal being output to an external device, and a capacitive device that is connected between a control voltage source and the floating diffusion region and, when a sensing operation of a corresponding pixel is terminated, deselects the pixel by altering the voltage of the floating diffusion region according to a control voltage provided by the control voltage source.

Abstract: A signal generation apparatus, a frequency converting apparatus and a receiver, in which the signal generation apparatus includes an oscillator, a duty cycle adjusting circuit, and a signal generation circuit. The oscillator generates differential signals. The duty cycle adjusting circuit adjusts duty cycles of differential output signals, in response to at least one of a plurality of control signals, to adjust phases of the differential output signals generated according to a result of amplifying a difference between the differential signals input through a pair of input terminals so as to output duty cycle adjusted differential output signals to a pair of output terminals. The signal generation circuit outputs an in-phase signal and a quadrature-phase signal in response to the duty cycle adjusted differential output signals.