Abstract: A one-time resealable protective kit for medical sharps has a stiff body which has a predetermined shape for initially packaging a medical sharps and for receiving the used medical sharp. The stiff body is designed so as to prevent the blade or needle of the medical sharps from piercing the stiff body. The protective kit has a resealable cover and a lower attachment mechanism that can be used to affix the protective kit to a table or other suitable surface. In operation, the protective kit is releasably secured to a table or other suitable surface by contacting the attachment mechanism to the surface. The user then peels back the cover of the protective kit to access the medical sharp. Once the medical sharp has been used, it is replaced into the body of the protective kit. The cover can then be closed over the body of the protective kit, effectively sealing the medical sharp inside the protective kit. The entire protective kit can then be safely disposed of in accordance with standard medical practices.

Abstract: The present invention is embodied in a memory system which restores full functionality to a dynamic random access main memory having at least one defective bit. In a preferred embodiment of the invention, the memory system is integrated on an industry standard memory module which is plugged into a host computer system. The memory module incorporates a block of DRAM main memory, an SRAM replacement memory, a non-volatile memory which stores a map of defective memory locations within the main memory, and a process control module (PCM) operable in multiple modes, which manages a defective address identification and replacement process. The PCM, which contains high-speed registers, in addition to decoding and control logic, is implemented as a high-speed application-specific integrated circuit (ASIC).

Abstract: This invention embodies a process for passivating the edges of a tungsten metal layer within a word line stack. After the word line stack is patterned (i.e., formed by masking and etching the stack of globally-deposited layers) as shown in FIG. 1, a conformal silicon film is blanket deposited. Deposition of the silicon film may be accomplished by any available technique, such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. The wafer is then heated so that the tungsten in contact with the silicon film is converted to tungsten silicide. In a preferred embodiment of the invention, only a portion of the silicon film is allowed to react with the edge of the tungsten layer. The remainder of the silicon film is converted to silicon dioxide by subjecting the wafer O.sub.2 in a furnace or rapid thermal processing chamber. Alternatively, the remainder of the silicon film may be converted to silicon dioxide by subjecting the wafer to O.sub.2 or O.sub.3 in a plasma reactor.

Abstract: This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. The focus of this invention is a CMOS manufacturing process flow which permits P-channel source/drain doping subsequent to capacitor formation. A main feature of the process is the deposition and planarization of a thick insulative mold layer subsequent to N-channel device patterning, but prior to P-channel device patterning. In one embodiment of the process, portions of this insulative layer overlying the P-channel transistor regions are removed during the storage-node contact etch.

Abstract: This invention is embodied in several variations of a process for independently forming both fixed and variable patterns within a single photoresist resin layer. In one application of the invention, both a fixed global alignment mark pattern and a variable identification mark pattern are formed in a single photoresist resin layer, and both patterns are transferred to an underlying substrate with a single etch step. Each pattern is formed independently of the other; the global alignment mark pattern by exposing the photoresist resin on a stepper device, and the identification mark pattern by either exposing or ablating the photoresist resin with a computer-controlled laser beam. Although this invention is described in the context of placing marks on a semiconductor wafer, the method is also applicable to other types of marks on other types of substrates.

Abstract: This invention is a process for depositing tungsten metal on a silicon surface with the deposited layer having improved uniformity of thickness over prior art deposition techniques. The process involves the steps of removing any native silicon dioxide present on the silicon surface, forming a barrier layer which overlies the silicon surface which prevents the upward diffusion of silicon atoms from the polycrystalline surface, and depositing a final tungsten metal layer on top of the barrier layer. The barrier layer is preferably a refractory metal nitride. It may be formed directly by chemical vapor deposition, by reactive sputtering, or it may be formed indirectly by depositing a preliminary tungsten metal layer, subjecting the preliminary layer to a plasma formed from NH.sub.3 and N.sub.2 gases. Both preliminary and final tungsten metal layers are deposited preferably via chemical vapor deposition using the WF.sub.6 and SiH.sub.4 as reactants.

Abstract: A process is disclosed for forming interconnect channels and contact vias using a single mask. The interconnect channels are formed in an upper silicon dioxide dielectric layer, while the contact vias are formed in both the upper dielectric layer and a lower silicon dioxide dielectric layer. A primary silicon nitride etch stop layer is sandwiched between the upper dielectric layer and the lower dielectric layer, and an optional secondary silicon nitride etch stop layer is sandwiched between a subjacent conductive region and the lower dielectric layer. A contact via/interconnect channel photomask is formed on top of the upper dielectric layer. The critical dimension of the contact via openings is about twice the critical dimension of the interconnect channel openings. A reactive-ion etch, that is selective for silicon dioxide over silicon nitride is performed, exposing the primary etch stop layer in the contact via openings, but not along the length of the interconnect channels.