Abstract: Restarting of coupling facility commands. A restart token is obtained from one coupling facility command and used to restart another coupling facility command. The command from which the restart token is obtained is a different command from the command being restarted. In one example, the command being restarted is a duplexed command.

Abstract: Assignment of a unique address identifier to a partition of a computing environment is provided by extending the applicability of hunt groups. A single-member hunt group is initiated to provide an alias address (e.g., hunt group ID) which is associated with the partition of the computing environment. A token (or token and password) facilitates the association between the alias address and the partition. Subsequent communication between the partition and a fabric switch of the computing environment will use the alias address as a source or destination address identifier, thereby uniquely identifying the partition.

Abstract: A virtual address is translated to a real address using one or more tables at varying levels. An entry of a table is indexed based in part on a table origin and a table offset. The virtual address includes one or more indexes corresponding to the one or more varying level tables. A table is addressed as a function of the table origin and the corresponding index in the virtual address. The table offset indicates the actual beginning of the table from the origin.

Abstract: A deterministic, non-deadlocking technique to achieving distributed consensus in a multithreaded multiprocessing computing environment is provided. A communicator is established across multiple processes in the multithreaded computer environment notwithstanding that multiple groups of threads may be simultaneously trying to establish communicators. The technique includes communicating across the multiple processes to establish a candidate identifier for the communicator for a group of participating threads of the multiple processes; and communicating across the multiple processes to check at each participating thread of the multiple processes whether the candidate identifier can be claimed at its process, and if so, claiming the candidate identifier as the new identifier thereby establishing the communicator. As one example, the technique can be implemented via a subroutine call within a message passing interface (MPI) library.

Abstract: A facility is provided to allow for dynamic configuration of data routing between TCP/IP stacks of multiple partitions of a multi-partition processing system and a network adapter such as a local area network (LAN) gateway for the multi-partition processing system. The facility includes a command for automatically providing the network adapter with information that a particular partition of the processing system is to function as a router; and using the information at the network adapter to forward data received across the network to the partition when the data is to an unregistered HOME internet protocol (IP) address. The forwarding of data to the router partition occurs without any conventional IP processing.

Abstract: Instruction and data registers of processors of a multiprocessing computing system are joined and forked to allow processing in multiple modes of operation. When joined, the registers of the processors each contain a same piece of information, hence generating single instruction and data streams. In contrast, when forked, the registers of the processors contain different pieces of information, thereby generating multiple instruction and data streams. Additionally, information may be stored into partitions of memory and fetched and broadcast by processors local to the particular memory sections thereby resulting in a faster cycle time.

Abstract: A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.

Abstract: Channel-to-channel communications is provided by integrating channel-to-channel functionality into one or more communication channels of a computing environment which may include heterogenous computer systems. The one or more channels having the integrated CTC function are non-dedicated channels also capable of conventional channel functionality. Work units at such channels are forwarded to either the CTC function or the channel function based on work unit type. Further, a facility is provided for. automatically deciding which of the first channel and the second channel is to provide the CTC function for a CTC connection. Partition-to-partition communication can also be accomplished using the integrated CTC function by establishing an internal logical path between a first logical partition and the CTC function and a second logical path between a second logical partition and the CTC function.

Abstract: A facility is provided to allow retrieval of specific parameters by a communications stack (e.g., TCP/IP) of a multi-partitioned processing system from a shared network adapter coupling the processing system to a network. The processing system includes multiple communications stacks, each of which registers internet protocol (IP) addresses with the network adapter in an address resolution table shared by the multiple communications stacks. The facility includes query request and reply commands for selectively retrieving specific data from the shared address resolution table, wherein the specific data can include: local registered IP addresses for a communications stack issuing a query request, network address resolution entries associated with a particular HOME IP address, HOME IP addresses of one or more other communications stacks sharing the network adapter, IP addresses owned by other entities on the network, IP addresses which are in the address cache, as well as other types of data.

Abstract: In a mainframe class data processing system having multiple logical partitions and a port to a network, a host-network interface is established for reducing network overhead at the multiple partitions. The host-network interface includes, for example, a host channel connection coupling the multiple partitions of the host system to a communications adapter having a network device driver for each network coupled to the adapter. The adapter also includes an address resolution protocol (ARP) cache designed to hold predetermined media headers for the clients coupled to the network(s) for use in forwarding an internet protocol (IP) datagram across the network to one of the clients from a partition of the host system. Provision is also made for partition-to-partition communication of IP datagrams by storing IP addresses of the logical partitions as HOME addresses in the ARP cache of the adapter.

Abstract: Asynchronous requests, such as input/output (I/O) requests, within a coprocessor of a computing environment are managed. The management of the asynchronous requests is based on priorities associated with the asynchronous requests. This management includes, for instance, selecting an asynchronous request to be processed using a priority scheme, and/or affording resources to the asynchronous requests using a priority scheme.

Abstract: Method, system and program storage device are provided for implementing a register pipe between processing engines of a multiprocessor computing system. A register pipe includes at least one first register of a first processing engine and at least one second register of a second processing engine. Data is transferred between the first processing engine and the second processing engine through the register pipe without passing through memory. In one embodiment, general purpose registers within the first processing engine and within the second processing engine are employed to implement the register pipe. A control mechanism is provided within each processing engine to dynamically enable or disable the register pipe coupling any two processing engines of the multiprocessor computer system. A technique for broadcasting to multiple register pipes and for implementing barrier synchronization using a register pipe addressed to a processing engine itself are also provided.

Abstract: A job scheduler module for a distributed processing system is provided with capability to protect jobs from planned or unplanned subsystem downtimes. The approach includes determining a downtime for a subsystem of the distributed processing system, determining at least one of a start time and an end time of a job to be executed using the subsystem, determining whether the start time or the end time of the job is within the downtime, and if not, placing the job in an eligible job list. The scheduler then makes a decision whether to start the job using the eligible job list. A downtime protection flag can be associated with each job, thereby allowing a user to indicate whether the job is to receive subsystem downtime protection. If not, then the job is placed directly in the eligible job list for scheduler execution irrespective of subsystem downtime.

Abstract: Synchronization “states” of programmable length imposed on processing nodes are disclosed, the last of which contains an event requiring action by fully synchronized nodes. The nodes are shifted between the states using a shared timing source to ensure synchronization for the event. The first state is a “non-impending event” state where the nodes continue their routine processing; the second state is an “impending event state” closer to the event, and within which nodes “wait” for the event by suspending their routine processing. In the third state, immediately preceding the final, event state, any non-waiting nodes are interrupted for the impending event. The present invention therefore allows some node autonomy during the first state within which the nodes poll at their leisure, and during the second, “wait” state, but during the third, interrupt state, any nodes not yet arriving by polling are interrupted.

Abstract: A coupling facility is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to be supported, including the duplexing of structures of the coupling facilities. Duplexing is performed on a structure basis, and thus, a coupling facility may include duplexed structures, as well as non-duplexed or simplexed structures.

Abstract: A central queue-based packet switch contains multiple input ports and multiple output ports coupled by a central queue path and a bypass path. The central queue has only shared memory and processing dynamically switches from transfer of message portions across the central queue path to the bypass path whenever a next message portion is identified by an output port as a critical portion. Upon transfer of message forwarding to the bypass path, subsequent message portions are forwarded across the bypass path unless the output port signals for transfer of the message portions back through the central queue path. Dynamic switching of message transfer from the central queue path to the bypass path is accomplished irrespective of whether contention exists for the output port.

Abstract: A backing out capability backs out a component of a computing environment, while maintaining the availability of the computing environment. In particular, a component of the computing environment which is associated with at least a portion of a unit of work is backed out from one version to another version. In addition, the backed out component is capable of emulating the other version.

Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which participated in a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.

Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which participated in a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.

Abstract: A semiconductor device, full bridge converter employing the same, and methods of fabrication thereof are provided. The device includes a vertical MOSFET having a parasitic body diode at a junction face between a body region and a semiconductor layer thereof. The parasitic body diode is suppressed by having no direct electrical connection to the body region, resulting in the parasitic body diode being open-circuited within the MOSFET. Co-packaged with the MOSFET is a separate bypass diode connected across a source and a drain of the MOSFET. The bypass diode functions to clamp the voltage across the MOSFET without employing the parasitic, electrically isolated body diode of the MOSFET.