Patents Represented by Attorney Fogg and Associates, LLC
  • Patent number: 6924963
    Abstract: An electrostatic discharge protection circuit for an integrated circuit that reduces unwanted transient currents during normal operations. In one embodiment, the electrostatic discharge protection circuit includes one or more electrostatic bus lines, a plurality of signal bonding pads and charge pumps. The one or more electrostatic bus lines are used to direct electrostatic discharge around internal circuitry. The plurality of signal bonding pads are used to receive external voltage signals. Each signal bonding pad is coupled to an associated electrostatic bus line via an unidirectional conducting device. A charge pump is used on each electrostatic bus line to precharge its associated electrostatic bus line to an associated predetermined voltage level.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: August 2, 2005
    Assignee: Intersil Americas Inc.
    Inventors: William R. Young, Gregg D. Croft
  • Patent number: 6919782
    Abstract: A cavity filter assembly is provided with at least one structural cavity wall comprising a circuit board. The circuit board may also contain other circuits and circuit elements such as trim capacitors, inductors, low noise amplifier circuits and power amplifiers that are part of the filter's function. Input and output coupling structures and connectors may also be provided on the circuit board. The circuit board may contain inter-stage coupling circuits, signal traces, and coupling pads/structures. Further embodiments are provided that incorporate test connectors and directional couplers on the circuit board. In yet other embodiments the filter's electrical characteristics are tunable with trim elements mounted on the circuit board, such as capacitors or inductors, in either mechanical or electrical manner. The filter's electrical characteristics may also be tunable with mechanical elements mounted through the circuit board.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: July 19, 2005
    Assignee: ADC Telecommunications, Inc.
    Inventors: David D. Sauder, Teppo Lukkarila
  • Patent number: 6919715
    Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: July 19, 2005
    Assignee: Intersil Corporation
    Inventors: Volodymyr A. Muratov, Michael Coletta, Wlodzimerz S. Wiktor
  • Patent number: 6920591
    Abstract: An error rate detector is provided. The error rate detector includes a sequence generator that is adapted to generate a test sequence for comparison with a received sequence. The error rate detector also includes a self synchronization circuit that is responsive to the test sequence received from the sequence generator and the received sequence. The self synchronization circuit is adapted to move the sequence generator to a different point in the sequence based on a measure of mismatches between the test sequence and the received sequence.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: July 19, 2005
    Assignee: ADC Telecommunications, Inc.
    Inventor: Donald R. Bauman
  • Patent number: 6909146
    Abstract: A silicon-on-insulator integrated circuit comprises a handle die, a substantially continuous and unbroken silicide layer over the handle die, and a substantially continuous and unbroken first dielectric layer overlying one side of the silicide layer. A device silicon layer having an upper surface overlies the first dielectric layer, and a second dielectric layer on the handle die underlies the opposite side of the silicide layer. Interconnected transistors are disposed in and at the upper surface of the device silicon layer. A silicon-on insulator integrated circuit includes a handle die and a first dielectric layer formed on the handle die. A substantially continuous and unbroken silicide layer is formed on the first dielectric layer; the silicide layer has a controlled resistance and provides a diffusion barrier to impurities.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: June 21, 2005
    Assignee: Intersil Corporation
    Inventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller
  • Patent number: 6902967
    Abstract: An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: June 7, 2005
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom
  • Patent number: 6900754
    Abstract: A method that can locate the center of a target even when the target is a large vehicle, and that, when a plurality of beams are reflected, determines whether the reflected beams are from the same target or not, wherein, of peaks generated based on a radar signal reflected from the target, peaks whose frequencies are substantially the same and whose reception levels are not smaller than a predetermined value are selected and, when a plurality of such peaks are selected, a center angle between the angles of the leftmost and rightmost peaks is obtained, and the thus obtained center angle is taken as an angle representing the target. Further, the plurality of peaks are paired up to detect a distance, relative velocity, and displacement length for each of reflecting points on the target, and when the differences in these values are all within respectively predetermined values, the plurality of peaks are determined as being peaks representing the same target.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: May 31, 2005
    Assignee: Fujitsu Tem Limited
    Inventors: Daisaku Ono, Masayuki Kishida
  • Patent number: 6898543
    Abstract: Testing an oscillator and other electronic devices on a circuit board. One method of the present invention comprises powering the oscillator. Providing test instructions to a microprocessor on the circuit board to place the microprocessor in a test mode. Receiving a clock signal from the oscillator at a multiplexer in a field programmable gate array. Receiving operating instructions at the multiplexer from the microprocessor. Multiplexing the clock signal to an external access port with the multiplexer in response to the operating instructions and measuring the frequency of the clock signal at the external access port.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: May 24, 2005
    Assignee: ADC DSL Systems, Inc.
    Inventors: Juan A. Espinoza, L. Grant Giddens, Clark Tollerson
  • Patent number: 6897103
    Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: May 24, 2005
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom
  • Patent number: 6897377
    Abstract: A receptacle for confining circuit cards to different locations within a housing and that has a frame is provided. The frame has an array of slots, each containing one of the circuit cards. In one embodiment, the receptacle has a cam that is selectively engageable with the frame for clamping the circuit cards within the frame. In another embodiment, a shaft is rotatably attached to the receptacle. The shaft has a head at one end and a nut opposite the head. A resilient element is disposed on the shaft between the head and the nut. The resilient element is axially compressible between the head and nut to bulge generally perpendicularly to the axial direction into engagement with the frame for clamping the circuit cards within the frame.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: May 24, 2005
    Assignee: ADC Telecommunications, Inc.
    Inventors: Gary Gustine, Charles Ham, Matthew Kusz, Michael Sawyer
  • Patent number: 6893221
    Abstract: A method for controlling fan operation that includes detecting a stopped fan and attempting to start the stopped fan. The method includes attempting to start the stopped fan again after at least one first time interval when the fan does not start. The method includes attempting to start the stopped fan again after at least one second time interval when the fan does not start after a predetermined number of first time intervals, where the at least one second time interval is longer than the first time interval.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: May 17, 2005
    Assignee: ADC DSL Systems, Inc.
    Inventors: Dennis Patrick Miller, Douglas G. Gilliland
  • Patent number: 6895089
    Abstract: Resistance in parallel with inductors in a series leg of the low-pass filter facilitates changing input and output resistance of the filter with little or no change in the reactance of the inductors. Furthermore, the reactance of the capacitors in the shunt legs of the filter will be substantially unaffected. This assists the designer in matching the impedance of the filter in the pass-band while still providing substantial impedance mismatching in the stop-band without substantially affecting the characteristics of the filter. Facilitating impedance matching in the pass-band and impedance mismatching in the stop-band is accomplished without the need for more complex active components. POTS splitters making use of such filters can facilitate impedance matching of line and load termination in a telecommunications system in response to signals within the frequencies of typical analog telephony service while providing impedance mismatching in response to signals within the frequencies of typical xDSL service.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: May 17, 2005
    Assignee: ADC DSL Systems, Inc.
    Inventor: Jie Dong Wang
  • Patent number: 6894349
    Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: May 17, 2005
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom
  • Patent number: 6894907
    Abstract: In one embodiment, a case for confining at least one circuit card to a location within a housing is provided. The case has at least one slot that contains the circuit card. The case also has at least one actuator adapted to clamp the circuit card within the slot.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: May 17, 2005
    Assignee: ADC Telecommunications, Inc.
    Inventors: Gary Gustine, Charles Ham, Matthew Kusz, Michael Sawyer
  • Patent number: 6885855
    Abstract: An amplification circuit for a wireless base station is provided. The amplification circuit includes a first port adapted to communicate signals to and from an antenna and a second port adapted to communicate signals to and from a base station. The amplification circuit further includes a first path and a second path with each path coupled between the first and second ports. The first path includes at least one bandpass filter and an amplifier that pass and amplify upstream signals in a first frequency band. The second path includes a filter that stops upstream signals in the first frequency band and passes upstream signals in at least a second frequency band and downstream signals in at least third and fourth frequency bands.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: April 26, 2005
    Assignee: ADC Telecommunications, Inc.
    Inventor: Esa Vuoppola
  • Patent number: 6882942
    Abstract: A power monitor circuit and method delays the start of a computer until multiple power lines are at a safe level of operation. The integrated circuit monitors only the voltage of a primary power supply output and eliminates the need for monitor circuits on each supply output. The power supply is made to exacting specifications that tie the 5 volt and 3.3 volt supplies to the primary 12 volt supply. The ATX power supply drives the 3.3 and 5.0 supplies to reach 90% of their values within 40 ms after the 12 volt supply reaches 90% of its value. A time delay circuit 25 delays switching the 3.3 and 5 volt dual outputs from the standby voltage supply to the active voltage supplies until after the primary 3.3 and 5 volt are at a safe operating level.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: April 19, 2005
    Assignee: Intersil Corporation
    Inventor: Bogdan M. Duduman
  • Patent number: 6873195
    Abstract: A clock compensation circuit is provided. The circuit comprises a clock synchronization circuit coupled to receive an input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals. The circuit further comprises a phase comparator coupled to receive one of the plurality of internal logic clock signals and a sample clock from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals and a down converter channel coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the internal logic clock signal based on the control signal.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: March 29, 2005
    Assignee: BigBand Networks BAS, Inc.
    Inventors: Paul Dormitzer, Willem Engelse, Raymond Robidoux
  • Patent number: 6867495
    Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: March 15, 2005
    Assignee: Intersil Americas Inc.
    Inventors: Joseph A. Czagas, Dustin A. Woodbury, James D. Beasom
  • Patent number: 6868332
    Abstract: A display system able to display a television screen and a navigation screen, giving due consideration to safe vehicle operation, provided with a screen switching unit for displaying a television screen instead of a navigation screen at least at part of a display screen during display of the navigation screen, a switching instructing unit for instructing switching to the screen switching unit when detecting that a predetermined event has occurred, or a screen area setting unit for setting a specific area in the screen for display by switching by the screen switching unit instead of the switching instructing unit.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: March 15, 2005
    Assignee: Fujitsu Ten Limited
    Inventor: Junji Hashimoto
  • Patent number: RE38780
    Abstract: A DC/DC converter has an output voltage and sources an output current to a load. The DC/DC converter includes an error amplifier with a reference input and a summing input. The reference input is electrically connected to a reference voltage. The summing input is electrically connected to the output voltage and the output current. The summing input is configured for adding together the output voltage and the output current. The error amplifier issues an error signal and adjusts the error signal dependent at least in part upon the output voltage and the output current. A comparator receives the error signal. The comparator has a ramp input electrically connected to a voltage ramp signal. The comparator issues an output signal that is based at least in part upon said error input. A power switch has an on condition and an off condition, and supplies dc current to the load when in the on condition. The power switch has a control input electrically connected to the comparator output signal.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: August 23, 2005
    Assignee: Intersil Americas Inc.
    Inventors: Charles E. Hawkes, Michael M. Walters, Robert H. Isham