Patents Represented by Attorney Fountain Law Group, Inc.
  • Patent number: 8350271
    Abstract: Disclosed is an RF power FET or HEMT including an electrically-conductive substrate, a grounding metallization layer disposed on a bottom surface of the electrically-conductive substrate, an active area comprising at least one cell including source, gate and drain electrodes disposed over a top surface of the electrically-conductive substrate, and an electrically-conductive shallow trench electrically connecting the source electrode to the grounding metallization layer by way of the electrically-conductive substrate. This configuration results in the effective RF ground being very close to the active area of the FET in order to reduce parasitic source inductance and resistance. This results in potentially higher gain, higher saturation point, higher 3rd-order intercept, more efficient combining of the input RF signal, and more efficient extraction of the output RF signal.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: January 8, 2013
    Assignee: Integra Technologies, Inc.
    Inventor: Gabriele F. Formicone
  • Patent number: 8344809
    Abstract: A radio frequency (RF) amplifier is disclosed including an active device adapted to amplify an input signal in accordance with a gain frequency response to generate an output signal, and a dissipative circuit adapted to modify the gain frequency response by dissipating the input or output signal more so at a first frequency range than at a second frequency range. The dissipative circuit may include a resistive element, and an open circuit adapted to operate as an open at a specified frequency to substantially minimize the dissipation of the input or output signal through the resistive element at the specified frequency. The open circuit may include an open-ended transmission line having an electrical length of a half wavelength or multiple thereof at the specified frequency. Alternatively, the open circuit may include a short-ended transmission line having an electrical length of a quarter wavelength or odd multiple thereof at the specified frequency.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: January 1, 2013
    Assignee: Integra Technologies, Inc.
    Inventor: Apet Barsegyan
  • Patent number: 8324822
    Abstract: An apparatus is disclosed that is capable of delivering substantially constant power to a luminous load with variation in the input voltage and the environment temperature. The apparatus may be further adapted to vary the power supplied to the luminous load based on changes in the input voltage produced by a phase control dimmer or external device. Additionally, if the input voltage is changed due to a user controlling a dimmer device to control the brightness of the luminous load, the apparatus is able to control the power delivered to the load in response to the dimmer device. Additionally, the apparatus is adapted to allow the luminous output light intensity to be controlled by changes in a remote control voltage source or variable resister and draws near unity power factor power from the AC input throughout the dimming range when not used with phase control dimmer. The remote control or variable resistor can operate simultaneously with a dimmer to achieve multiple controls for the light output.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: December 4, 2012
    Assignee: Ace Power International, Inc.
    Inventor: Chunghang Peng
  • Patent number: 8299857
    Abstract: An RF power amplifier is disclosed that has improved input matching or reduced return losses over a wider frequency range. The amplifier includes an input impedance matching network, a resistive element, a transistor, and an output impedance matching network. The resistive element is coupled between the input impedance matching network and the input of the transistor. The resistive element is configured to lower the quality factor (Q) of the input impedance matching network. This has the effect of reducing the input impedance variation over a given frequency range. As a result, the overall impedance matching over the given frequency range is improved, thereby reducing the input return losses. This allows the RF power amplifier to be used in wider bandwidth applications.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: October 30, 2012
    Assignee: Integra Technologies, Inc.
    Inventor: Richard P. Keshishian
  • Patent number: 8168286
    Abstract: A glass chair mat and method of packaging comprising a sheet of tempered glass with rounded corners and rounded beveled edges. The tempered glass chair mat may be finished to enhance its appearance or left translucent to showcase the flooring underneath. The method of packaging allows a minimal amount of employees to safely package the glass chair mat for delivery to residence and businesses alike. Furthermore, the packaging provides additional protection against damage during transit and assures common carriers are aware of the fragile nature of the package.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: May 1, 2012
    Assignee: KBJ Enterprises, LLC.
    Inventor: Kenneth B James
  • Patent number: 8167090
    Abstract: An apparatus is disclosed for safely lowering a user from a structure. The apparatus includes a frame; a spool including a cable rotatably mounted on the frame; a securing device attached to the cable and adapted to securely attached to the structure; a user support adapted to support the user and securely attached to the frame; and a pair of centrifugal hydraulic brake systems adapted to slow a rotation of the spool to cause the user support, spool and frame to descend at a safe rate for the user. In another embodiment, the apparatus includes a frame; a spool including a cable rotatably mounted on the frame; a securing device attached to the frame and adapted to securely attached to the structure; a user support adapted to support the user and attached to the cable; and a pair of centrifugal hydraulic brake systems adapted to slow a rotation of the spool to cause the user support to descend at a safe rate for the user.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: May 1, 2012
    Inventor: Ralph L. Michael
  • Patent number: 8028382
    Abstract: A child safe fastening device including a clip, one or more than one padded layer covering one or more surfaces of the clip and one or more than one cover layer secured to the padded layer. The clip, the padded layer, and the cover layer form a plush device.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: October 4, 2011
    Inventor: Adrienne Alitowski
  • Patent number: 7855845
    Abstract: An optical control system including a mount for an optical component is disclosed that provides the flexibility of independently adjusting the position and orientation of the optical component along and about one or more axes. In an exemplary embodiment, the mount includes a support element for supporting the optical component; one or more rotational adjustment elements for rotating said support element independently about one or more axes, respectively; and one or more linear adjustment elements for moving said support element independently along one or more axes. The adjustment elements may be manually adjustable and/or may be adjustable by an actuator. In the latter case, the actuator may be electronically controlled by a controller. The optical component may be a reflective, transmissive, or reflective/transmissive optical device, such as diffraction gratings, mirrors, beam splitters, and others.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: December 21, 2010
    Assignee: Newport Corporation
    Inventors: Michael Heuser, Christopher Guerrero
  • Patent number: 7835186
    Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: November 16, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
  • Patent number: 7835184
    Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: November 16, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
  • Patent number: 7816967
    Abstract: An apparatus for generating a pulse having a pulse width substantially independent of process variation in resistive and capacitive values. The apparatus includes a PTAT current source to generate a first current to charge a capacitor to produce a first voltage; a ?VGS current source to generate a second current through a resistor to produce a second voltage V2; a comparator to generate the pulse in response to the first and second voltages; and a circuit to enable the charging and discharging of the capacitor. The use of the distinct current sources (e.g., PTAT and ?VGS) enables the pulse generator to be configured substantially process independent of resistive value. The use of a MOSFET capacitor for the capacitor enables the pulse generator to be made substantially process independent of capacitive value. An additional bandgap current source in parallel with the ?VGS current source reduces the pulse width dependency on temperature.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: October 19, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Karthik Nagarajan, Mustafa Ertugrul Oner
  • Patent number: 7795716
    Abstract: An RF/microwave circuit is configured to eliminate the physical constraint that requires a sacrifice of one output series inductor wirebond for each shunt inductor wirebond. The circuit employs a multi-level metalized substrate as part of its output impedance matching network. The lower level of the multi-level substrate serves as an intermediate connection point for the output series inductor wirebonds as it extends from the output terminal of an active device to an output metallization pad. The upper level of the multi-level substrate serves to support a DC block capacitor and as an intermediate connection point for the shunt inductor wirebonds. The multi-level substrate allows the series inductor wirebonds to be positioned at a lower height, and the shunt inductor wirebonds at a greater height. Because they are at different heights, the physical constraint of sacrificing a series wirebond per a shunt inductor wirebond can be eliminated.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: September 14, 2010
    Assignee: Integra Technologies, Inc.
    Inventors: Jeffrey A. Burger, Fouad F. Boueri
  • Patent number: 7791955
    Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: September 7, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
  • Patent number: 7729607
    Abstract: Various image-capturing systems are disclosed that use polarized filters to reduce or control glare effects on captured images. In one embodiment, the system includes a light source, a first polarized filter adapted to polarize light emanating from the light source; a second polarized filter adapted to perform polarized filtering on received light; and an image-capturing device adapted to receive the filtered light. In another embodiment, the system further includes an actuator to selectively move any of the polarized filter into and out of the light path. In yet another embodiment, a method of forming a resultant image comprises recording a first image with a filter set to a first polarization angle, recording a second image with the filter set to a second polarization angle, and blending the first and second images. The recording of the first and second images may be performed simultaneously or at different times.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: June 1, 2010
    Assignee: Technologies4All, Inc.
    Inventor: John H. Karim
  • Patent number: 7716793
    Abstract: A child safe fastening device comprises a clip, one or more than one padded layer covering one or more surfaces of the clip and one or more than one cover layer secured to the padded layer. The clip, the padded layer, and the cover layer form a plush device.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: May 18, 2010
    Inventor: Adrienne Alitowski
  • Patent number: 7688528
    Abstract: A mount for an optical component is disclosed that provides the flexibility of independently adjusting the position and orientation of the optical component along and about one or more axes. In an exemplary embodiment, the mount includes a support element for supporting the optical component; one or more rotational adjustment elements for rotating said support element independently about one or more axes, respectively; and one or more linear adjustment elements for moving said support element independently along one or more axes. The adjustment elements may be manually adjustable and/or may be adjustable by an actuator. In the latter case, the actuator may be electronically controlled by a controller. The optical component may be a reflective, transmissive, or reflective/transmissive optical device, such as diffraction gratings, mirrors, beam splitters, and others.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: March 30, 2010
    Assignee: Newport Corporation
    Inventors: Heuser Michael, Guerrero Christopher
  • Patent number: 7675166
    Abstract: An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The enclosure encapsulates an integrated circuit die which is electrically coupled to the first and second electrical contacts. The alignment insensitive first and second electrical contacts may be electro-mechanically connected to corresponding contacts of an end-use equipment (e.g., a printer). Further, the integrated circuit package may be hosted by a peripheral device (e.g., a printer cartridge).
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: March 9, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Jeff Alan Gordon, Steven N. Hass, Hal Kurkowski, Scott Jones
  • Patent number: 7675544
    Abstract: A video circuit including a video amplifier adapted to generate an amplified output video signal from an input video signal; a short detection circuit adapted to generate a first signal indicative of whether there is a short present at an output of the video amplifier; and a load detection circuit adapted to generate a second signal indicative of whether there is a load coupled to the output of the video amplifier. The video circuit may further include an input signal detection circuit adapted to generate a third signal indicative of whether an input video signal is present. The third signal generated by the input signal detection circuit may be used to enable the outputting of the first and second signals in order to prevent the false indication of faults at the output of the video amplifier in the absence of an input video signal.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: March 9, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ronald Bonshaw Koo, Michael David Petersen
  • Patent number: 7535389
    Abstract: An apparatus and method for reducing distortion from an output of a digital-to-analog converter (DAC). In one implementation, the distortion being reduced is third order harmonic distortion caused by charge transfer effects and instantaneous output impedance drop during switching. Each of the embodiments includes a module adapted to generate a distortion correction signal being a function of the input digital signal, the full scale code of the DAC, the load resistance, the conversion rate of the DAC, and a proportionality constant. In another implementation, the distortion being reduced is higher order harmonic distortion caused by timing skew between a main DAC and a least significant bit (LSB) DAC. Each of the embodiments includes a module adapted to generate a distortion correction signal being a function of the input digital signal, the number of levels covered by the LSB DAC, the conversion rate of the DAC, and the timing skew.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: May 19, 2009
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Jerzy Antoni Teterwak
  • Patent number: 7505503
    Abstract: A vertical cavity surface emitting laser (VCSEL) is disclosed that has a relatively low vertical resistance between the Ohmic contact to the upper distributed Bragg reflector (DBR) and the active layer, and a structure to substantially confine the current flow to the laser cavity so that the VCSEL can produce a more efficient and substantially single-mode output. In particular, the VCSEL includes a substrate, a lower DBR disposed over the substrate, an active layer disposed over the lower DBR, and an upper DBR. The upper DBR includes a groove and an Ohmic contact situated within the groove to lower the vertical resistance between the contact and the active layer. An ion implanted layer is also formed along the side wall of the active layer to substantially confine the current flow to the laser cavity.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: March 17, 2009
    Assignee: Cosemi Technologies, Inc.
    Inventors: Nguyen X. Nguyen, Charles F. Krumm