Abstract: An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits.

Abstract: An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits.

Abstract: In a projection apparatus for projecting optical images, an optical mask support stage having a pair of separated arms. Each arm being provided with a respective mask chucking bar that supports a respective edge of a thin glass mask and applies to the respective edge a bending moment away from the center of the mask to reduce or eliminate any gravitational induced sag in the center of the mask thereby improving the quality of the images projected by the apparatus.

Abstract: An apparatus and a method for testing semiconductor devices such as integrated circuits having a handler for picking up an integrated circuit to be tested and placing the picked up integrated circuit into an automatic circuit test apparatus. When the circuit to be tested is inserted into the test apparatus an extraneous signal shield is automatically engaged to enclose the device being tested and protect the circuit, being tested, from stray extraneous electromagnetic signals during the test thereby preventing said stray electromagnetic interference from inducing errors in the tested circuit.

Abstract: A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.

Abstract: A semi-conductor module burn-in test apparatus having a plurality burn-in boards each of which is provided a plurality of module test sockets thereon and each test socket is coupled to an adjacent test socket by with a high current, open/short split power connector that can readily connected to or disconnected from said adjacent test socket by coupling together the power inputs of the adjacent sockets or uncoupling the previously coupled power inputs of adjacent sockets and thereby selectively altering the current carrying levels available to said adjacent test sockets.

Abstract: A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.

Abstract: A semiconductor wafer chemical mechanical treatment apparatus having a sectional extended arm carrying a head. The sectional arm is comprised of a fixed yoke and an elongated arm positioned in said yoke on a pivot. The elongated arm carries a first means thereon for establishing and maintaining a given loading or pressure on the head. A second means, is positioned on the yoke, adjacent to the elongated arm for temporarily altering the given loading or pressure on the head established by the first means without disturbing the setting of the first means such that when the second means is reset the given head load or pressure established by said first means is automatically restored.

Abstract: An assembly, including a tool for measuring an applied force and its centroid relative to the center of the tool. A method of measuring and adjusting a force and its centroid applied to a semiconductor chip in a socket by an abutting heat sink consisting of the steps of inserting the tool in the socket, applying a heat sink on the tool, measuring the applied force and its centroid with respect to the center of the tool, adjusting the heat sink until the centroid of the applied force is substantially aligned with the center of the tool, removing the heat sink and tool, from the socket, substituting a semiconductor chip for the tool and reapplying the heat sink whereby the centroid of the force applied by the heat sink is substantially aligned with the center surface of the semiconductor chip in the semiconductor device.

Abstract: A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.

Abstract: An ion generator chamber, for an implantation apparatus, having its interior walls surfaces knurled or roughened so that any of the materials used in the chamber cannot deposit onto the interior wall surfaces in a size sufficiently large enough to adversely affect the operation of the chamber, if the deposits peel off the interior walls of the chamber. By limiting the size of any deposits on interior chamber walls, the invention extends the average life of the filaments used in the chamber as well as extending the average time between any necessary cleaning of the inner chamber walls thereby extending the operating life of the chamber.

Abstract: A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip.

Abstract: This is a circuit and protocol for relaxing the strobe to data relationship to permit the writing into and reading out of a double data rate DRAM array at data transfer rates higher than any known circuits that utilize a strobe and data protocol. This result is accomplished by modifying the prior art write circuitry by adding a strobe generator coupled to both the data input and the strobe input to control the write circuit multi-latch and by modifying the prior art read circuit by coupling the initial and enable circuit to the data drivers and adding a data compare circuit that is coupled between the memory storage array and the strobe toggle to control the strobe. In this way the present invention relaxes the use of the strobe to data relationships for reads and writes except when there are no data transitions and ends the necessity of aligning the strobe with the data eye.

Abstract: The disclosed invention relates generally to electronic data storage systems that access data storage memory modules via a data bus comprised of multiple data query lines and, more particularly, to an electronic data storage system provided with a data bus that can be selectively provided with terminations thereby permitting the data storage memory to use either modules that require that the data query lines be open-ended, i.e., without terminations or modules that require that the data bus be terminated and to a method for operating such a system. The present invention is particularly directed to a single memory system that can accommodate either 3.3V DIMMs or DDR DIMMs. This is especially accomplished by providing the processor circuit, used in memory storage systems, with both (3.

Abstract: The disclosed invention provides a reduction of voltage noise or bounce in logic chips and does so in a practical way without requiting additional circuit elements that impact on circuit performance or speed. Broadly this reduction in voltage bounce is achieved by forcing the unused Input/Output (I/O) circuits, i.e., those chips not being activated, to serve as alterative paths to the voltage power supply used by the switching circuits. More particularly this is accomplished this by grouping the I/O points on the chips into logical, functional units such as data buses, control lines, the I/O points on switched circuits, i.e., those switched at high frequency and the I/O points on static circuits, i.e., non-switched and interconnecting and using the I/O points on the static circuits and the power supply drives coupled thereto as alternate pats to the power supply used by the switched circuits.

Abstract: A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data.

Abstract: A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip.

Abstract: An integrated circuit capacitor device that increases capacitance without proportionately using more substrate surface area. Uniquely, the capacitor uses up to all four sides of the first charge plate to store charge by surrounding it with a second charge plate with an insulator layer separating the two plates.

Abstract: This is a semiconductor chip package configuration particularly suited for stacking. These described arrangement is especially adapted to be used with the so-called Lead-On-Chip type package. Each package is of minimum size, and provided with a thermal heat sink arranged with respect to the remainder of the package to balance the stresses induced in the package during fabrication. This is accomplished by placing a lead frame on the active face of the semiconductor chip, bonding the lead frame conductors to respective input/output pads on the active face of the chip, and molding an encapsulant completely around five of the six sides of the chip but leaving a substantial portion of the sixth side unencapsulated. A heat sink is affixed on the exposed, i.e. unencapsulated, portion of the sixth side of the chip.

Abstract: A method of locating a predetermined variation in the surface of a film such as selected depression or elevation on a film deposited on a surface and for measuring the depth of the depression or height of the elevation comprising the steps of establishing a datum plane based on the average level of the surface of the film, scanning the surface of the film with a laser beam until a predetermined variation from said datum plane is located, on the surface of the film, incrementally stepping the laser beam around and across the located variation, measuring the beam reflected at various points along the variation to determine the contour of the variation by establishing the slope of the variation between various measurements, establishing the apex of an elevation or bottom of a depression by determining when the measured slope goes to zero, and measuring the height of the established apex or depth of the established bottom of the depression with respect to the established datum plane of the film.