Abstract: Building a package for installing a software application on a data processing system with a distributed architecture is provided. The installation package is built using an authoring tool based on a declarative model. A descriptor is used to define a desired configuration of the system. The installation package is built declaring a discoverer element, a producer element and a consumer element into the wizard tree. During the installation process, the discoverer element detects a current configuration of the system. The producer creates a working queue dynamically, inserting the installation operations that are needed for reaching the desired configuration from the current configuration of the system. The producer then executes the installation operations defined in the working queue. In this way, the installation operations are determined at runtime.

Abstract: The present invention provides for a system for computer program code size partitioning for multiple memory multi-processor systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A program representation based on received computer program code is generated. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one SESE region of less than a certain size (store-size-specific) is identified based on identified SESE regions and the at least one system parameter. Each store-size-specific SESE region is grouped into a node-specific subroutine. The non node-specific parts of the computer program code are modified based on the partitioning into node-specific subroutines. The modified computer program code including each node-specific subroutine is compiled based on a specified node characteristic.

Abstract: A method and apparatus are provided for calibrating digital thermal sensors. A processor chip with a plurality of digital thermal sensors receives an analog voltage. A test circuit coupled to the processor chip receives a clock signal and a register coupled to the test circuit outputs a value on each clock cycle to a digital thermal sensor in the plurality of digital thermal sensors. The digital thermal sensor transitions an output state in response to the value of the register received in the digital thermal sensor equaling a temperature threshold of the digital thermal sensor. The value of the register at the point of transition is used to calibrate the digital thermal sensor. An incrementer increments the value of the register on each clock cycle in response to the value of the register received in the digital thermal sensor failing to equal the temperature threshold of the digital thermal sensor.

Abstract: A medium and system for managing an external routine in a computer implemented database management system includes creating a first table for storing external routines in a data store coupled to the database management system. An external routine is stored in the first table so that the database management system is allowed to automatically manage any modification related to the external routine and to control access to the external routine such that administrative support is minimized.

Abstract: Monitoring performance of dynamic web content applications, including receiving, at run time, by a monitor agent, data corresponding to each one of a previous verification point and a current verification point; determining, by the monitor agent, whether decision criteria are satisfied, wherein the determining includes comparing the data corresponding to the previous verification point and the data corresponding to the current verification point; and if the decision criteria are satisfied replacing, by the monitor agent, the data corresponding to the previous verification point with the data corresponding to the current verification point.

Abstract: A system for communicating command parameters between a processor and a memory flow controller is provided. The system makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A method for managing an external routine in a computer implemented database management system includes creating a first table for storing external routines in a data store coupled to the database management system. An external routine is stored in the first table so that the database management system is allowed to automatically manage any modification related to the external routine and to control access to the external routine such that administrative support is minimized.

Abstract: A method for sharing memory locations in a virtual memory system is disclosed. The method can include processing instructions and accessing data utilizing a virtual memory system with a paging device that is accessible by multiple clients. The method can also include configuring a first client to access the paging device, configuring a second client to access the paging device and allowing the first and second client to access the paging device via a virtual input output server. Other embodiments are also disclosed.

Abstract: A method for enhancing the memory bandwidth available through a memory module of a memory system is provided. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

Abstract: An example of a solution provided here comprises receiving a signal for sending in a side conversation, and in response to the signal for sending, sending a first portion of text, in a side conversation. The first portion of text is new, and the first portion of text is not necessarily revealed to some participants.

Abstract: A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

Abstract: A mechanism is provided for transmitting data from a first processor of a data processing system to a second processor of the data processing system. In one or more switches, a set of virtual channels is created, the one or more switches comprising, for each processor, a corresponding switch in the one or more switches. The data is transmitted from the first processor to the second processor through a path comprising a subset of processors of a set of processors in the data processing system. In each processor of the subset of processors, the data is stored in a virtual channel of a corresponding switch before transmitting the data to a next processor. The virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted.

Abstract: Illustrative embodiments of the invention provide for managing a computer network. One illustrative embodiment forms a first representation of a network element as a physical entity in an information model, the first representation having a form independent of an implementation defined by a vendor; and maps a portion of the first representation from the information model to a second representation in a vendor-independent data model residing in a first repository, the second representation having a form suitable for use with the first repository.

Abstract: Performing scalar operations using a SIMD data parallel execution unit is provided. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution unit. The scalar operations are converted, such as by a static or dynamic compiler, into one or more vector load instructions and one or more vector computation instructions. In addition, control words may be generated to adjust the alignment of the scalar values for the scalar operation within the vector registers to which these scalar values are loaded using the vector load instructions. The alignment amounts for adjusting the scalar values within the vector registers may be statically or dynamically determined.

Abstract: Compressing transaction data is provided. A current transaction data point is received. A determination is made as to whether the current transaction data point is a first transaction data point or a subsequent transaction data point of a set of transaction data points for a current variable length aggregation record. A further determination is made as to whether the subsequent transaction data point is within a predetermined tolerance of a predicted transaction data point in response to the current transaction data point being the subsequent transaction data point. The subsequent transaction data point is compressed into the current variable length aggregation record in response to the subsequent transaction data point falling within the predetermined tolerance of the predicted transaction data point.

Abstract: Aspects of the invention provide a method, system and computer program product for managing multiple user identities for a user of an electronic commerce (e-commerce) site. The method comprises defining the e-commerce site as one or more security domains; and in response to a user's request to invoke an operation of the e-commerce site: determining a one of the one or more security domains to which the operation relates; performing one of a) creating a session and b) reusing a session for the user automatically in accordance with the determined security domain, said session associated with a user identity and a role indicating privileges for invoking operations of the e-commerce site in at least the determined security domain; and persisting said session for reuse. The user's request may be received in association with one or more sessions persisted for the user and a one of the sessions selected in accordance with the determined security domain. In response, either a session may be created or reused.

Abstract: A mechanism is provided for distributing software features (particularly software products having a global portion and a user portion necessary for activating the software products) to client workstations of a network. Each client workstation has a multi-user operating system that may be accessed with different user profiles, each one associated with a corresponding operating context. A distribution package is received in the client workstation; the distribution package includes instructions associated with global activities for the client workstation as a whole or with user activities specific for the single profiles. A distribution agent (running outside the context of a current profile) executes only the global activity and schedules the user activities to be performed when a user next logs onto the workstation. A user agent loaded when the workstation is accessed with a selected profile executes the user activities in the corresponding context.

Abstract: A mechanism is provided for providing a native code library from a server to an application written in an interpreted programming language for execution on a remote computer. An installer object is invoked from within a main class of the interpreted programming language application. The install object extracts a file list from the server including at least one native code library filename indicating a native code library. The native code library indicated by the native code library filename is installed to a target directory on the remote computer and the main class of the interpreted programming language application is then invoked on the remote computer. Additional native code library dependencies are also installed to the target directory on the remote computer.

Abstract: Registering memory space within a data processing system is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. At least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.

Abstract: A memory system is provided that manages thermal conditions at a memory device level transparent to a memory controller. The memory systems comprises a memory hub device integrated in a memory module, a set of memory devices coupled to the memory hub device, and a first set of thermal sensors integrated in the set of memory devices. A thermal management control unit integrated in the memory hub device monitors a temperature of the set of memory devices sensed by the first set of thermal sensors. The memory hub device reduces a memory access rate to the set of memory devices in response to a predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the set of memory devices.