Abstract: A semiconductor device comprising a semiconductor chip having an active and a passive surface, the passive surface adhesively attached to a substrate film by means of a multilayer composite; this composite comprising a metal foil having first and second surfaces and an adhesive layer attached on each of these surfaces. The multilayer composite has an average modulus larger than the modulus of the encapsulating molding compound used in the semiconductor device. By applying the composite to assembling face-up chip-scale devices, stress in solder joints is reduced and solder fatigue life enhanced.

Abstract: A method of operating a communication circuit comprises the steps of receiving a plurality of signals (508-509, 514-516) from a plurality of remote transmitters (502-506) and determining which of the plurality of remote transmitters use transmit diversity. A signal strength of each respective signal of the plurality of signals is calculated. One of the remote transmitters is selected in response to the steps of determining and calculating.

Abstract: Disclosed is a lighted wafer cassette for use in semiconductor wafer processing. Also disclosed are systems and methods employing a wafer cassette lighted with one or more affixed light sources for facilitating cassette alignment with standard semiconductor processing apparatus.

Abstract: A sigma-delta ADC includes a higher order infinite impulse response (IIR) filter based on a finite impulse response (FIR) filter and possesses the same functionality as a conventional sigma-delta ADC in terms of noise and swings at the output of the analog integrators. The higher order sigma-delta ADC requires only one analog amplifier however, even though it has a higher order analog integration function.

Abstract: Pipeline activity information associated with all stages of execution of an instruction in an instruction pipeline of a data processor is presented to an event detector in timewise aligned format. This permits events in the pipeline to be presented to the event detector in a sequence that is consistent with the context in which a programmer of the event detector would normally think of those events, thereby simplifying programmation of the event detector.

Abstract: An embodiment of the instant invention is a method of oxidizing a first feature (feature 108 and/or feature 104 of FIG. 1 and feature 314 of FIG. 3) while leaving a second feature substantially unoxidized (features 110 and 112 of FIG. 1 and features 310 and 312 of FIG. 3), the method comprised of subjecting the first and second features to an oxygen-containing gas and a separate hydrogen-containing gas. Preferably, the oxygen-containing gas is comprised of gas selected from the group consisting of O2, N2O, CO2, H2O, and any combination thereof, and the hydrogen-containing gas is comprised of H2. The first feature is, preferably, comprised of polycrystalline silicon, silicon oxide, or a dielectric material, and the second feature is, preferably, comprised of tungsten.

Abstract: A output driver architecture (100) is proposed that uses thin gate-oxide core and thin gate-oxide Drain-extended transistors that can directly interface with voltage supplies up to six times the normal rating of the transistor. A bias generator (101), level shifter (103) and output stage (105) are adapted to buffer an input signal with a voltage swing of less than the normal operating voltage of the transistors to an output signal with a voltage swing of up to approximately six times the normal operating voltage of the transistors. The bias generator is interfaced directly with a high voltage power supply and generates a bias voltage with a magnitude of less than the dielectric breakdown of the transistors internal to the level shifter and output stage.

Abstract: An interpolation for a Bayer pattern color filtered array with red and blue interpolation using weightings as ratios of corresponding green pixel values.

Abstract: An embodiment of the invention is a method of manufacturing a semiconductor wafer 2 where a layer of undoped silicon glass 15 is formed over the front-end structure 3. Another embodiment of the present invention is an integrated circuit 2 having a back-end structure 4 in which the dielectric layer 15 contains undoped silicon glass.

Abstract: Emulation communications via a test access port and boundary-scan architecture providing serial access to a serial connection of a plurality of registers disposed in a plurality of modules. One of the modules is selected for communication. Nonselected modules are made nonresponsive to data on the serial connection. The external emulation hardware supplies a serial signal having a first logic state for a number of cycles greater in number than a number of bits of the serial connection of registers to the test access port. The emulation hardware supplies a start bit having an opposite logic state. The selected module detects the start bit and stores the next predetermined number of data bits. These bits could be data bits to be stored in a program visible data register or bits interpreted as an instruction for execution by the module. The selected module may transmit return communications via the serial scan path using the same format.

Abstract: The semiconductor memory device has a memory capacity that can be increased without increasing the load to bit lines and has increased access speed. Because the output lines of bit line selector circuits 20 through 27 are precharged by charge circuits 30 through 37, and selectable bit lines (SBL, SBLZ) reach a high level before access is gained for reading from memory cells, data read previously is held unchanged for output signal SAOUT of data latch circuit 70. Because output lines of bit line selector circuits 20 through 27 are all at the high level even when another gate circuit becomes conductive as a new read address is set, the selected bit lines remains at the high level, and data previously read is held unchanged for output signal SAOUT of data latch circuit 70. Output signal SAOUT of data latch circuit 70 is changed to the next data read as soon as differential amplification operation of the bit lines is completed by amplifier circuits 40 through 47.

Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

Abstract: A method of forming a first and second transistors with differing work function gates by differing metals deposited to react with a silicon or silicon-germanium gate layer.

Abstract: A mechanism for implementing time tracking and early/ontime/late correlation processing in a vector correlator has been implemented to accommodate processing of data when the earliest chips in a triple data input buffer are to be processed and time tracking needs to be done to an earlier sample and further to accommodate processing of data when chips being processed are the last chips in a circular input buffer and time tracking needs to be done to a later sample.

Abstract: A method of reducing dopant losses is provided. The method includes providing a transistor structure having a first region, implanting a dopant into the first region, depositing a control layer adjacent the first region, and performing a first annealing process on the transistor structure. The control layer is operable to prevent at least a portion of the dopant in the first region from diffusing out of the first region toward the control layer during the first annealing process.

Abstract: A method (70) of operating a wireless receiver (UST). The method receives a wireless communicated signal, wherein the signal comprises asymmetrically spaced synchronization channel components. The method also defines (72) a set of signals from the communicated signal, wherein the set spans a number of equal duration time slots and comprises at least a first synchronization channel component and a second synchronization channel component. The method also forms (76) a first signal combination by combining a first portion of the set of signals with a second portion of the set of signals, and it forms (78) a second signal combination by combining a third portion of the set of signals with a fourth portion of the set of signals. Finally, the method detects (80, 82, 84) a location of the first synchronization channel component and a location of the second synchronization channel component in response to at least one of the first and second signal combinations.

Abstract: A low-cost, high-performance, reliable micromirror package (300) that replaces the ceramic substrate in conventional packages with a printed circuit board substrate (30) and a molded plastic case (33), and the cover glass with a window (36), preferably an optically clear plastic window. The printed circuit board substrate (30) allows for either external bond pads or flex cable connection of the micromirror package to the projector's motherboard. These packages support flexible snap-in, screw-in, ultrasonic plastic welding, or adhesive welding processes to overcome the high cost seam welding process of many conventional packages.

Abstract: A system for signal boosting includes a capacitance boosting component that contains a first and second transistor and a capacitor, wherein a positive terminal of the capacitor is electrically connected to a drain of the second transistor and a negative terminal of the capacitor is electrically connected to a source of the first transistor. The system also includes a third transistor operable to receive a clock signal. A drain of the third transistor is electrically connected to the positive terminal of the capacitor. A fourth transistor is operable to receive an inverse of the clock signal. A drain of the fourth transistor is electrically connected to the positive terminal of the capacitor. The system further includes a boost component electrically connected to the capacitance boosting component wherein an output of the boost component is within a selected boost voltage range.

Abstract: A data processing system is provided with a digital signal processor which has an instruction for conditionally branching based on the contents of a specified test register. Each time a branch is taken, the register is decremented as a side effect of executing the branch instruction. In addition, a predicate register is specified by the instruction. A branch occurs only if both registers meet specified conditions.

Abstract: A low-cost, high-performance, reliable micromirror package (300) that replaces the ceramic substrate in conventional packages with a printed circuit board substrate (30) and a molded plastic case (33), and the cover glass with a window (36), preferably an optically clear plastic window. The printed circuit board substrate (30) allows for either external bond pads or flex cable connection of the micromirror package to the projector's motherboard. These packages support flexible snap-in, screw-in, ultrasonic plastic welding, or adhesive welding processes to overcome the high cost seam welding process of many conventional packages.