Abstract: A post-assembly trim of a monolithic IC is set forth wherein selected package pins can be employed to address the on-chip trim circuit. Then, after the trim is completed, the circuit is addressed to provide a disconnect of the coupling between the trim pins and the post assembly trim circuit of the IC, while leaving the pins fully usable for other purposes. This means that following the post-assembly trim the trim pins cannot accidentally be employed for further trimming and the packaged IC is user-proof. A circuit that employs zener zapping for both trimming and disconnect is detailed and the invention is clearly usable for plastic encapsulated devices. However, when cavity containing packages are involved it is shown that a combination of zener zapping and fuse blowing can be employed.

Abstract: An automotive voltage regulator is disclosed to have plural regulated outputs using a transient protected isolator output stage (TPIOS) that prevents a system fault condition on any one output from adversely affecting the other outputs. In an automotive environment employing a nominal 14-volt supply, an individual output can be taken from -4 to +26 volts without causing damage or having any significant reaction on the non-faulted outputs. The circuit employs a relatively small NPN output pass transistor and, therefore, requires a relatively low value stabilizing bypass capacitor.

Abstract: A gauge circuit for use with a wide angle air core meter display having high linearity and adapted for use with a remote sensing resistor. A constant sense current is provided and its value is moudlated at a frequency that is high with respect to the frequencies associated with offset voltages that occur with a sense resistor that is grounded remotely from the gauge ground. A low duty cycle pulse modulation shape is disclosed for the purpose of minimizing electromagnetic interference radiation.

Abstract: A trim arrangement for adjusting a differential input stage in a BIFET.RTM. integrated circuit is presented wherein the trimming is done at wafer probing in the manufacturing process. Trim JFETs are invoked by means of reverse biased zener diodes which can be zapped thereby to achieve trimming in the conventional manner. The trim JFETs are ratioed in size so that the trim is V.sub.P compensated over a relatively broad range. An improved trim structure is presented wherein the offset trim is V.sub.P compensated and operated in a manner that renders its effect on the circuit constant and independent of the conventional load trim.

Abstract: Current mode logic configuration circuits are shown for use with linear integrated circuit chips. The circuits employ plural collector lateral transistors to provide logic current source outputs in response to logic current inputs that are accepted by NPN transistor current mirrors acting as current sinks. Conventional logic functions are detailed and a toggle flip-flop configuration is shown being composed of the basic logic gates. Since the disclosed current mode voltage swings are small the circuit speed is relatively high at a given shunt capacitance. Die surface area is low with many transistors sharing common n-epitaxial tubs.

Abstract: A H-bridge circuit is disclosed using DMOST switches having current sensing parallel connected elements. An op-amp control circuit is coupled to the power and sense sources to force the sense source to the same potential as the power source. The op-amp circuit drives FET output devices which produce an output current proportional to the H-bridge current. A high voltage op-amp configuration is set forth.

Abstract: A circuit is described for reducing the skew between a pair of signal lines in a digital system. Before the two lines display a change in signal the circuit senses whether the signals are similar or different. If similar, the two lines are clamped together in true fashion. If different, the two lines are clamped together complementarily such that the signals remain mutually inverted.

Abstract: A DMOST driver circuit responds to the current flowing in the DMOST and the voltage appearing across it. The current and voltage are multiplied together in a g.sub.m amplifier which is coupled to drive a first input of a diff-amp. The diff-amp has its second input coupled to a source of reference potential. The diff-amp output is coupled to the DMOST gate to create a stabilizing negative feedback loop. The first diff-amp input is also coupled to a reference potential related threshold voltage so that the drive to the DMOST will be controlled by the DMOST power dissipation multiplied by a predetermined constant which is chosen to provide a safe dissipation level.

Abstract: A TTL inverter buffer circuit is provided with a switched current that produces hysteresis in the threshold values. The current is switched on by a control circuit when the input logic is low and off when the logic is high. The control circuit receives its sense from the logic state so that when the input logic is low a high threshold is created and when the input logic is high a low threshold is created. The difference is the circuit hysteresis voltage which is dependent upon the switched current and a resistor.

Abstract: A combined CMOS/linear circuit employs a voltage reference circuit to provide a temperature compensated V.sub.REF output. The circuit includes means for switching the reference circuit off and on in response to the signal on an enable terminal. The voltage reference circuit includes a current mirror feedback which is positive in nature to provide a controlled hysteresis action. This provides noise immunity for the enable input. A digital output indicator is included to indicate the state of the reference circuit.

Abstract: An improved process is described for the formation of PNP transistor collector base junctions or PN junction capaciters in silicon monolithic integrated circuits that employ the ion implantation and diffusion of aluminum in these regions that are to contain high performance PNP transistors or capacitors. The process reduces or eliminates the leakage typically found in such devices.

Abstract: A CMOS oscillator is disclosed using an inverter in which a pair of control terminals are employed to invoke various sized devices which control the flow of current. The inverter gain is determined by the size of the CMOS devices employed. A tuned circuit coupled to the inverter causes it to oscillate at the frequency of parallel resonance. The control terminals are coupled to the inverter invoke transistors that are sized as desired to establish the current flow and gain in the inverter. The current flow is controlled to optimize the gain of the inverter in terms of the frequency of oscillation. A Schmitt trigger can be employed to clean up the oscillator output for digital clock source applications.

Abstract: When ceramic packages are subjected to lead plating the solutions can reduce the glass oxides and produce metallization of the sealing glass. At best, this metallization is unsightly and at worst results in lead shorting. Such metallization can be greatly reduced or avoided by a pretreatment that passivates the glass. The pretreatment comprises an immersion in an aqueous solution of fluoboric acid or ammonium bifluoride. Improved solutions that additionally contain a wetting agent and other additives are disclosed.

Abstract: A process is disclosed for forming high-performance high-voltage PNP transistors in a conventional monolithic, planar, PN junction isolated integrated circuit that contains high-performance NPN transistors. The process permits independently optimizing the NPN and PNP transistors.

Abstract: A voltage regulator circuit is set forth in which the series pass transistor has its high impedance (collector/drain) electrode connected to the output terminal and a shunt transistor has its low impedance (emitter/source) electrode connected to the output terminal. The circuit is arranged to ensure that the shunt transistor is always conductive so that its low impedance electrode will stabilize the operation of the circuit without requiring any external components. The circuit can be fabricated in either bipolar or CMOS form and a low dropout configuration is employed.

Abstract: A circuit is shown in which a voltage regulator has an output stage that operates as a Darlington when the input-output differential exceeds a threshold. The circuit automatically switches to a common emitter output and an emitter-follower driver when the differential falls below the threshold. A current limiter prevents excessive common current when the output transistor is saturated.

Abstract: A Darlington output stage is shown in which the saturation voltage is reduced to the level of a single common emitter output transistor. The circuit includes a lateral feed-forward transistor that bridges the driver transistor. A resistor is included to ensure that the driver transistor is turned off when the output transistor saturates. An IC version of the circuit is set forth in detail.

Abstract: In a semiconductor device tape assembly bonding process the fingers of a copper tape are reflow soldered to metal bumps located on the semiconductor device. First, the semiconductor wafer is covered with a conductive film composed of thin layers of alumimum, nickel-vanadium alloy and gold. The bumps are then created by electroplating gold through openings in a photoresist mask. The gold bumps are overcoated with a controlled thickness tin layer and the tin is overcoated with a thin gold anticorrosion layer. The copper assembly tape is coated with a thin gold layer and are lightly pressed against the bumps by means of a thermode. The thermode is quickly heated to a temperature well above the gold-tin eutectic melting temperature and then rapidly cooled. The tin layer on the bump will combine with the adjacent gold to form a liquid phase eutetic which will form and contact both the copper finger and the gold bump. Upon cooling the eutectic melt will solder the finger to the bump.

Abstract: A CERDIP housing is provided with a heat pipe that passes through the closure seal lid whereby the heat pipe terminates within the housing cavity at the hot end thereof. A quantity of working fluid, such as fluorinated octane, is contained within the package cavity. The heat pipe communicates with cooling fins that produce a cold end thereof. Heat from the semiconductor device inside the housing boils the working fluid and is cooled thereby. The fluid vapor passes along the heat pipe and is condensed at the cold end to be converted back to liquid. As a result the semiconductor device is in direct communication with the heat pipe working fluid.

Abstract: A process is disclosed for forming high-performance, high voltage PNP and NPN power transistors in a conventional monolithic, planar, epitaxial PNP junction isolated integrated circuit. The process permits independently optimizing the NPN and PNP power trransitors. Where high-voltage devices are desired a field threshold adjustment implant is applied. It also includes provisions for testing critical portions of the process at appropriate points.