Abstract: A computer system architecture includes a processor for processing data, a memory for storing at least macroinstructions for use by the processor, microinstruction logic for storing and providing sequences of frequently used microinstructions, and busses for transmitting at least macroinstructions between the processor and memory. Microinstruction memory circuitry stores microinstructions in segmented form in available microinstruction memory space. Microinstruction segment by segment selection circuitry effects the selection of successive microinstructions of sequences of microinstructions.
Abstract: Therein is disclosed high speed digital computer system architecture. System architecture includes a processor for processing machine language digital data and a memory for storing at least machine language instructions for use by the processor. Instructions or data are transmitted between memory and processor by memory input and output busses. Signals are transmitted between computer system and external devices by I/O apparatus. Instruction pre-fetch circuitry is disclosed for fetching from memory, and storing, instructions in advance of instructions being executed by the processor. Also disclosed are a high speed memory and memory input and output busses providing high memory bus bandwidth and simple memory bus interface circuitry. Processor circuitry is disclosed for allowing high speed initiation and execution of instruction sequences. I/O circuitry is disclosed which allows I/O apparatus to easily adapt to a variety of external devices or to changes in computer machine language or instructions.
Abstract: Apparatus useful for loading and securing a boat onto a vehicle. Apparatus includes a mounting bolt attached to an end of the boat; mounting bolt having a shaft extending outwardly from the boat and an enlarged head at the outer end of the shaft. A horizontal, tubular bracket is mounted at one end of the vehicle; the bracket has a longitudinal opening extending therethrough, and a longitudinal slot in an upper wall. Mounting bolt engages the bracket with the bolt head within the longitudinal opening. A catch selectively retains the mounting bolt within a midportion of the bracket, or allows the bolt to pass longitudinally along the bracket to an end thereof to engage or disengage the bracket. In further embodiments, the slot is widened adjacent the bracket ends, to allow the mounting bolt head to pass vertically through the slot to engage and disengage the bracket, and stops prevent the mounting bolt from passing longitudinally out of the openings in the bracket ends.
Abstract: There is disclosed a circuit for providing a comparison signal representing phase relationship between a clock pulse train and a variable rate input pulse train. The comparison signal can be used to synchronize clock and input pulse trains. The circuit includes a phase difference measuring circuit providing a first signal proportional to phase difference between input pulse train and clock pulse train, the signal having related discontinuities at the points of minimum and maximum phase difference between input and clock pulse trains. A second signal is generated representing a selected value of phase difference, the selected value being greater than the minimum phase difference and less than the maximum phase difference. First and second signals are then compared to provide a signal representing difference between the measured and selected values of phase difference.