Abstract: For controlling the attitude of the body of an earth satellite placed on a low orbit, values of components of the geomagnetic field of the earth are measured along three axes of a frame of reference bound to the body. The values are derivated with respect to time, and multiplied by a gain. Currents responsive to the multiplicated derivatives are passed through magnetic torquers located along the three axes of the body to create magnetic torques that bias the body to a fixed angular position relative to the field lines of the geomagnetic field. Such steps are continuously carried out during eclipse periods. Out of eclipse periods, the pitch of the body is controlled by modifying an internal momentum in response to a signal provided by a solar sensor, so as to maintain solar generators carried by the body of the satellite oriented towards the Sun.

Abstract: A structure of double level metal free of voids is fabricated by depositing an insulating layer on the planarized layer which results from the growth of selective oxide layers to the thickness of the first metal wirings in the presence of the photoresist film patterns that are used to form the first metal wirings on the lower oxide layer. In addition, a patterning step for a second metal layer deposited on the insulating layer can be carried out with ease by virtue of the planarized layer of the first metal wirings, giving rise to a significant increase in the production yield. Thus, it can be usefully applied for ultra large scale integration devices, which are under a design rule of less than 0.4 .mu.m.

Abstract: A bit line sense amplifier driving circuit of a semiconductor memory device which has first and second refresh cycle functions includes a bit line sense amplifier driver unit for supplying a pull-up bias potential signal and a pull-down bias potential signal to a bit line sense amplifier; a bit line sense amplifier predriver unit for controlling the current flowing to the bit line sense amplifier driver unit; and a bit line sense amplifier predriver control unit for controlling the bit line sense amplifier predriver unit according to the first and second refresh cycle functions.

Abstract: A photo mask capable of reducing the time taken to carry out a process margin test and a method for performing a process margin test using the photo mask. The method includes the steps of preparing a wafer, coating a photoresist film over the wafer, performing a light exposure and development process for the photoresist film using a photo mask over which a plurality of unit patterns each consisting of three different process margin patterns are arranged, thereby forming a photoresist film pattern, and comparing an image of the photoresist film pattern with data about the process margin patterns of the photo mask stored in a CAD, thereby performing a process margin test.

Abstract: A semiconductor device and a method for fabricating the same, wherein a thick side wall oxide film or polysilicon film is formed on the edge portion of the second silicon substrate. At the side wall of the oxide film or polysilicon film, the thickness of an active semiconductor substrate at its edge portion increases, thereby obtaining an increased threshold voltage at the edge portion. That is, the formation of the side wall oxide film is carried out to prevent a gate oxide film of the semiconductor device from being directly formed on each side wall of the active silicon substrate. As a result, it is possible to prevent a degradation in electrical characteristic due to a degradation in threshold voltage caused by a reduced thickness of the active semiconductor substrate at its edge portion.

Abstract: A phase shift mask for forming contact holes arranged in longitudinal, transversal and diagonal directions, capable of achieving an improvement in light contrast in the formation of contact holes, thereby forming a fine contact hole pattern. The phase shift mask includes a shifter formed on a transparent substrate and patterned to define windows respectively arranged at contact hole regions where the contact holes are formed. The windows consist of first windows each having a central portion defined by a portion of the shifter and an edge portion defined by an exposed portion of the substrate arranged around the portion of the shifter, and second windows each having a central portion defined by an exposed portion of the substrate and an edge portion defined by a portion of the shifter arranged around the exposed portion of the substrate.

Abstract: A method for forming a tungsten wiring, wherein an etch barrier layer is formed on an area where a metal wiring will be formed, using chlorine-based plasma so that the etch barrier layer is used as a mask upon forming a metal wiring, thereby eliminating a limitation on the thickness of the tungsten junction layer. the method includes the steps of sequentially forming a tungsten junction layer and a tungsten film over a semiconductor substrate, forming a negative type photoresist film pattern using a metal wiring mask, forming a copper thin film on a selectively exposed portion of the tungsten film, growing the copper thin film in a chlorine-based plasma atmosphere, thereby forming a copper chloride thin film, removing the photoresist film pattern, sequentially etching the tungsten film and tungsten junction layer using the copper chloride thin film as a mask, and removing the copper chloride thin film, thereby forming a tungsten wiring.

Abstract: A skating appliance or vehicle having a skate with a plastic base and a composite running blade exchangeably secured thereto. The exchangeable composite running blade is secured with the high resistance to torsion and flexure as well as high security against fracture, by means of an on edge mounted profiled stabilizing rail set into the lower side of the base, and easy to handle screwable holding members, and a corresponding design of the individual parts. These elements allow an arrangement to be obtained which as a whole has a low weight and a high resistance to pressure.

Abstract: There are disclosed methods for the fabrication of semiconductor device. A junction leakage or defect which is generated at the bird's beak of field oxide film when forming an oxide film spacer at the side wall of a gate electrode in a MOSFET can be prevented by implanting a low density dopant or by sequentially implanting a high density dopant and a low density dopant into the substrate, subsequent to formation of the oxide film spacer.

Abstract: A redundancy circuit for a semiconductor memory device, comprising a first precharge transistor for transferring a precharge voltage to a first node in response to a first precharge signal, a second precharge transistor for transferring the precharge voltage transferred by the first precharge transistor to the first node in response to a second precharge signal, a first inverter for inverting a signal at the first node, an output terminal for transferring an output signal from the first inverter externally, a first NMOS transistor for transferring a supply voltage to the first node in response to a signal at the output terminal, a second inverter for inverting the second precharge signal, a second NMOS transistor for transferring a ground voltage to a second node in response to an output signal from the second inverter, a third NMOS transistor for transferring the ground voltage to the second node in response to the signal at the output terminal, a plurality of fourth NMOS transistors connected in parallel be

Abstract: A bit line sense amplifier array for a semiconductor memory device which has a memory cell array with at least two memory cells sharing a metal strapping region, and a plurality of true and complementary bit lines for transferring data from the at least two memory cells externally or transferring external data to the at least two memory cells. The bit line sense amplifier array comprises at least one sense amplifier block for sensing and amplifying data on the true and complementary bit lines.

Abstract: A method for testing an overlay occurring in a semiconductor device to compensate for an error generated in the measurement of overlay. This method involves forming an inner mark on a semiconductor wafer, and forming an outer mark on the semiconductor wafer in such a fashion that the outer mark is inclined in one direction and has an island portion arranged in the inside of the inner mark and a land portion comprised of a photoresist film pattern formed over the entire surface of the semiconductor wafer while being spaced from the island portion by a desired distance, thereby forming an overlay measuring mark consisting of the inner and outer marks. Measured values of the island and land portions of the inner mark are averaged and then compared with measured values of the outer mark, thereby deriving overlay compensation values. Accordingly, even if the overlay measuring mark is formed in an inclined state, the method can simply measure an inaccuracy in measured overlay value.

Abstract: A pulse signal transfer unit employing post charge logic, comprising a buffering circuit for transferring data with a specified logic value through a data transfer line, a PMOS transistor for supplying a voltage from a voltage source to the data transfer line to initialize a signal on the data transfer line, and a feedback loop circuit for applying the signal on the data transfer line to the PMOS transistor for one of the first and second time periods in response to an external write drive signal to control the PMOS transistor, the second time period being longer than the first time period. According to the present invention, in the case of accessing read data with a relatively narrow pulse width and write data with a relatively wide pulse width, the pulse signal transfer unit initializes the read data at a relatively high speed and the write data at a relatively low speed to provide a signal with a wider pulse width.

Abstract: A light exposure mask which is used in the formation of a micro pattern, including a transparent substrate, a chromium pattern formed on the transparent substrate, and assistant patterns formed on portions of the chromium pattern where a rounding effect is generated. By virtue of the assistant patterns, it is possible to prevent the phenomenon that the pattern is reduced in size due to the rounding effect. Accordingly, it is possible to accurately form a pattern having a desirable size. Each assistant pattern has a bar, inverted-triangular or inverted-U shape.

Abstract: This invention provides a device for capacitively measuring the distance to an object, which comprises an electrode that will couple capacitively with the object, a shield that surrounds the electrode and is electrically isolated from the electrode by means of insulation, and a layer of insulation that surrounds the shield, wherein the insulation between the electrode and the shield, and the insulation that surrounds the shield, are formed by deposition.This invention further provides a method for measuring the distance to a solid object, which comprises forming an electrode that will capacitively couple with the object, depositing a layer of insulation over at least part of the electrode so that the insulation surrounds the electrode, depositing a layer of metal over the insulation to form a shield, and depositing a second layer of insulation over the shield.

Abstract: A phase shift mask provided with an alignment error measuring pattern which is a phase shift film pattern portion formed in a space defined between dense patterns of the phase shift mask having an alternating type pattern structure so that an error in alignment between a chromium pattern and a phase shift film pattern occurring in the fabrication of the phase shift mask can be measured by checking, through a microscope, a wafer provided with a pattern formed using the phase shift mask. The phase shift film pattern portion is arranged on the central portion of a quartz substrate.

Abstract: The semiconductor memory device having a cell array of a folded bit line structure according to the present invention comprises main bit lines MB1 and MB2 and m sub-bit lines SB1i and SB2i (1.ltoreq.i.ltoreq.m), which detect amplifiers connected to both ends of the main bit lines, respectively, two sub-bit line block selection switching means for connecting the main bit line with respective sub-bit lines according to a block selection signal SBi, and a main bit line separation switching means connected between the two sub-bit line block selection switching means, for dividing the main bit line into two equal parts according to a main bit line separation signal. The number of cells connected to the bit lines is increased and the number of whole detect amplifiers is decreased, which may reduce the size of the chip so as to reduce the fabricating costs of the memory product.

Abstract: With the recognition that like esterase, the thiazole derivatives show a strong nucleophilicity owing to sufficient electronic density in heterocycle, when its ester is degraded by some enzymes. The composition for detecting leucocyte and proteinase in urine has been developed, which contains a thiazole derivative. According to this invention, the thiazole derivative may be synthesized as an ester form by combining both the well-known thiazolone derivative and amino acid derivatives as starting materials. Now that the method for manufacturing the thiazole derivative is simple and general, the mass-scale production may be available within a short period of time. Further, in case of the measuring device produced according to this invention, the application method is simple and diagnostic performance is superior.