Abstract: A new and improved translation circuit that accepts TTL signals and converts them to ECL levels while performing an AND/NAND function is provided, comprising at least two emitter-coupled transistor pairs, each coupled to an input terminal for receiving corresponding TTL signals and coupled to one another for performing the AND operation. Each emitter-coupled pair is also coupled to a bias drive for providing reference voltages that designate which one of each of the transistor pairs conducts, depending upon the state of the TTL signal received.

Abstract: The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region.

Abstract: A reference voltage generator including a circuit for generating a reference voltage V.sub.REF having a non-linear voltage-temperature function, in which the improvement comprises an additional resistor being in circuit to make the function linear. By making the function linear, the equation defining V.sub.REF is easily differentiated to determine the change in voltage with temperature.

Abstract: An improved circuit for serial scan diagnosis is provided. A state register in the signal path of the digital system under diagnosis is coupled to a diagnostic shift register. Test data is introduced and removed through the diagnostic shift register through a serial input terminal and serial output terminal. For certain operations the serial input terminal becomes a control terminal whereby a minimum number of control lines is required.

Abstract: A redundant semiconductor memory device is arranged in columns of bit cells addressable in bit segments with a plurality of separate, redundant, columns of bit cells, each separate column being capable of electronic placement at any column position within any bit segment of the memory. Specifically, multiplexer is provided at the output buffers of a memory for multiplexing conventional bit segments with spare columns of bit cells, wherein the spare columns are only activated, that is, selected, when a particular column in the conventional bit segment has been identified to be defective.

Abstract: A processor, used in microcomputer systems for performing data processing functions, includes an arithmetic-logic unit having three operand inputs to provide the capability of executing, in addition to typical arithmetic and logic operations, complex three-operand instructions in a single clock (instruction) cycle.

Abstract: A semiconductor wafer masked with a masking layer having an opening therethrough exposing a portion of the wafer which is to be etched to form a depression of a desired depth is etched via a first plasma etching step under high bias voltage-high energy conditions with a plasma which includes chlorine and a shape modifier species, e.g., argon, to a first depth which is less than the desired depth. Thereafter, the depression is treated by a second plasma etching step under low bias voltage-low energy plasma etching conditions with a plasma which includes chlorine and is substantially free of the shape modifier species. A wet chemical etch follows to remove damaged silicon and impurities. The resulting depression has relatively straight walls and is relatively free of cusps and apexes. The depression is formed quickly and has a desired shape while only a minimal amount of damage and impurities are introduced into the wafer.

Abstract: A voltage reference circuit design which is temperature compensated to the second order is presented. The circuit comprises a sub-circuit for generating a bandgap voltage reference temperature compensated to the first order and a sub-circuit having a differential amplifier for generating a current having a second order temperature dependency. The current in turn is used for generating a correction voltage having a second order temperature dependency. The first order band gap voltage reference and the correction voltage are combined to provide the second order temperature compensated band gap voltage reference.

Abstract: An improved substrate bias generator is disclosed for use in a capacitive charge storage integrated circuit memory device having an external voltage supply. The generator comprises means for generating first and second timing signals, charge pumping means disposed for pumping positive charge from the substrate of the integrated circuit memory device in response to the first and second timing signals. Removal of the positive charge from the substrate polarizes the substrate at a negative potential, which is the generated bias voltage. A voltage regulation means is disposed between the output of the charge pumping means (i.e., the substrate) and the means for generating the timing signals. The voltage regulation means provides a reference potential that regulates the amount of charge pumped from the substrate as a function of the magnitude of the generated bias voltage.

Abstract: A microprogram controller, in a microcomputer system used as an address sequencer intended for controlling the sequence of execution of microinstructions in a microprogram memory, is presented. The microprogram controller includes architecture that provides the capability to asynchronously receive indications of an event, break from the microinstruction sequence in response, branch to control of subroutine consisting of a predetermined microinstruction sequence directed to responding to the event, and returning to the interrupted sequence upon completion of the subroutine.

Abstract: The present invention provides a bus protocol interface circuit for the peripheral units that prevents a conflict in bus requests between the peripheral units and permits bipolar drivers to be used for fast operation. The interface circuit comprises a logic means coupled to the bus acknowledgment line input terminal and the bus acknowledgment line output terminal for generating a logic output signal responsive to the signals on the bus acknowledgement line input and output terminals, and latching means coupled between the bus request line and the bus request line terminal, and further connected to the output of the logic means and the bus acknowledgment line output terminal, for latching into a state consistent with a bus request signal from any one of the peripheral units and for unlatching from the consistent state upon receipt of a bus acknowledgment signal in response to the bus request signal.

Abstract: An asynchronous FSK modulator-demodulator (modem) having a capability of operating at data rates of 300, 600 and 1200 bits per second in a voiceband telephone channel is compatible with the specifications of the Bell 103/113, Bell 202, CCITT V.21 and CCITT V.23 modem types. The modem according to the invention is incorporated into a single integrated circuit to minimize external components in a system. The modem is pin programmable, that is, the mode and speed of operation is defined by a parallel digital data signal applied to device terminals. Digital signal processing techniques are employed to perform all major functions, including modulation and filtering. Multiplication functions are performed without need for multipliers by employing shift registers and canonic sign arithmetic. Analog-to-digital conversion and digital-to-analog conversion circuits are incorporated into the device.

Abstract: In source-clocked type of cross-coupled latch sense amplifier of a dynamic random access memory device, there is provided a sense clock that employs multiple extended dummy memory cells to provide reference timing which tracks time constants of word line, cell transfer gate, cell capacitor, and bit line, and the sense clock is further compensated over large variations of fabrication process parameters and operating conditions. The trigger and slave clock circuit are chained in series to control the timing sequence of a plurality of clocked output signals. The clocked output signals are selectively amplified and summed in parallel to generate current with an intended dynamic characteristic. The current so generated is applied to the common source electrodes of the cross-coupled latch.

Abstract: A current source for voltage regulators used in integrated emitter coupled logic (ECL) circuits to avoid variations in output current due to fluctuations in the voltage source. Transistors of one polarity type are employed. A current source (11) is connected to an output node (15). A transistor (Q2) generates a current proportional to the output voltage (15) to develop a voltage across a resistor (12) in turn controlling a transistor (Q3) in series with a resistor (14) and a diode connected transistor (Q4). By current mirror action the current flowing in transistor (Q4) is mirrored (I.sub.Q1) by transistor (Q1). The output current (I.sub.0) is the current flowing through resistor (11) less the current (I.sub.Q1).

Abstract: Method of forming buried contact in recessed gate MOSTEK technology is provided. When the buried contact is desired, a MOS transistor is formed and the gate and underlying gate oxide layer removed to expose the substrate. A conducting layer through the aperture formed makes contact to the substrate.

Abstract: In a digital data communication receiver, an apparatus for estimating the time of zero-crossing between successive samples of a continuous frequency shift keyed (FSK) or like zero-crossing signal in a manner more accurate than is provided by the basic sampling clock. The apparatus includes means for sensing a change in sign relative to successive samples of the signal and means responsive to the sensed sign change to interpolate between the values of the respective samples for indicating more accurately the time of occurrence of the zero-crossing prior to the second sample, thereby demodulating the continuous signal.

Abstract: A unitary logic circuit for performing the function of an EXCLUSIVE OR logic gate, the output terminal of which forms a first input terminal to an AND logic gate. Implemented in emitter-coupled logic technology, the circuit has a fast response time with low power consumption.

Abstract: A high speed, low power, latching, difference amplifier giving Feedback Emitter Coupled Logic level output voltages. The comparator operates with low voltage swings between logic levels to minimize propagation delay and heat dissipation. Efficiency is aided by diverting unneeded current away from the input stage to the latch stage during the latch enabled state, and the input slew rate to the comparator is effectively increased by clamping the input terminals with Schottky diodes. The amplifier works on a restricted common mode range, and normally has its reference voltage input grounded, although other reference voltages may be used. The output can be either positive or negative true. Propagation delay is under 4 nanoseconds, minimum sensitivity is 5 millivolts, and heat dissipation is under 50 milliwatts.

Abstract: An apparatus and method for generating a specific sequence of addresses of values of an array stored in a digital memory. The addresses are generated by a first counter which generates a seed value and a second counter which generates a control value, the control value controlling a bit inserter and a programmable shifter to set, respectively, the bit place position of bit insertion and the amount of shift. The output of the bit inserter is the row position of related addresses for butterfly operation of a fast Fourier transform array. The output of the shifter is the address of coefficients associated with the complex rotation of the butterfly operation. The apparatus is an integrated circuit intended for use as a modular integrated circuit in connection with digital memory means and central processing means including a digital multiplying means.

Abstract: A programmable device for signal processing applications in which short loops of digital data are processed repetitively and in parallel. The device consist of five independently programmable subsystems whose functions are able to operate simultaneously. The apparatus is intended for use in a connection with a digital multiplier device and a digital memory device for such signal processing applications as fast Fourier transforms and time domain filtering in real time or near real time. The five parallel functions are1. to move data in and out of an external memory device between selected registers;2. to move data in and out of an external multiplier between selected registers and an arithmetic logic unit (ALU);3. to move data from the output of a multiplier to selected registers and to the ALU;4. to propagate data selectively through a chain of registers, the chain being of preselectable length; and5. to perform selected arithmetic and logic operations.