Abstract: The present invention discloses a novel layout and process for a device with segmented BLM for the I/Os. In a first embodiment, each BLM is split into two segments. The segments are close to each other and connected to the same overlying bump. In a second embodiment, each BLM is split into more than two segments. In a third embodiment, each segment is electrically connected to more than one underlying via. In a fourth embodiment, each segment is electrically connected to more than one underlying bond pad.

Abstract: The present invention describes an aperture comprising an opaque plate with a central opening and at least one peripheral opening and a method for combining an on-axis component and at least one off-axis component of illumination light.

Abstract: Alloy memory structures and methods are disclosed wherein a layer or volume of alloy material changes conductivity subsequent to introduction of a electron beam current-induced change in phase of the alloy, the conductivity change being detected using current detection means such as photon-emitting P-N junctions, and being associated with a change in data bit memory state.

Abstract: The present invention discloses a method including providing a substrate; forming a dielectric over the substrate, the dielectric having a k value of about 2.5 or lower, the dielectric having a Young's modulus of elasticity of about 15 GigaPascals or higher; forming an opening in the dielectric; and forming a conductor in the opening. The present invention further discloses a structure including a substrate; a dielectric located over the substrate, the dielectric having a k value of 2.5 or lower, the dielectric having a Young's modulus of elasticity of about 15 GigaPascals or higher; an opening located in the dielectric; and a conductor located in the opening.

Abstract: The present invention describes a method for creating a differential polish rate across a semiconductor wafer. The profile or topography of the semiconductor wafer is determined by locating the high points and low points of the wafer profile. The groove pattern of a polish pad is then adjusted to optimize the polish rate with respect to the particular wafer profile. By increasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be increased in the areas that correspond to the high points of the wafer profile. By decreasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be decreased in the areas that correspond to the low points of the wafer profile. A combination of these effects may be desirable in order to stabilize the polish rate across the wafer surface in order to improve the planarization of the polishing process.

Abstract: The present invention discloses a method including providing a substrate; forming a dielectric material over the substrate; forming an opening in the dielectric material; treating a surface of the dielectric material; forming a conductor in the opening; and planarizing the conductor. The present invention further discloses a structure including a substrate; a dielectric material located over the substrate, the dielectric material having a low dielectric constant; an opening located in the dielectric material; a treated layer located over a sidewall of the opening; and a conductor located in the opening and over the treated layer.

Abstract: The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning.

Abstract: The present invention describes an apparatus comprising a mask; a pellicle spacer, the pellicle spacer attached to the mask; and an electrostatic pellicle system, the electrostatic pellicle system attached to the pellicle spacer. The present invention further describes a method of keeping contaminants away from a vicinity of a mask during exposure, the contaminants including an uncharged or neutral particle, a positively-charged particle, or a negatively-charged particle, comprising: inducing a positive or negative charge on the uncharged or neutral particle; attracting the positively-charged particle with a negatively-charged electric field; and attracting the negatively-charged particle with a positively-charged electric field.

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Abstract: The present invention discloses an EUV mask having an improved absorber layer with a certain thickness that is formed from a metal and a nonmetal in which the ratio of the metal to the nonmetal changes through the thickness of the improved absorber layer and a method of forming such an EUV mask.

Abstract: The present invention discloses a method of fabricating and repairing a mask without damage and an apparatus including a holder to mount a substrate; a stage to position the holder in a chamber; a pumping system to evacuate the chamber; an imaging system to locate an opaque defect in the substrate; a gas delivery system to dispense a reactant gas towards the defect; and an electron delivery system to direct electrons towards the opaque defect.

Abstract: A wafer passivation structure and its method of fabrication is described. According to one embodiment of the present invention a metal layer having a bond pad spaced by a gap from a metal member is formed on a substrate. A first dielectric layer is then formed over the bond pad and the metal member and completely fills the gap. Next a second dielectric layer, having a dielectric constant greater than the first dielectric layer and being hermetic is formed over the first dielectric layer. In another embodiment of the present invention a first dielectric layer is formed on the top surface of a bond pad of a substrate. A second dielectric layer is then formed on the first dielectric. An opening is then formed through the first and second dielectric layers so as to expose the top surface of the bond pad. A barrier layer is then deposited on the sides of the opening and on the top surface of the bond pad. A contact is then formed on the barrier layer in the opening.

Abstract: The present invention claims a binary mask printing a product feature which includes a narrow space; and a phase-shifting mask having an assist feature that fits within the narrow space when both masks are properly aligned in exposing a wafer.

Abstract: In accordance with one embodiment of the invention, a method of compressing a color image includes the following. The wavelet transform of each of the respective color planes of the color image is computed. One of the respective wavelet transformed color plane frames is encoded. For the other two respective wavelet transformed color plane frames, a prediction coefficient from at least one of subbands of each color plane thereof is computed. In accordance with another embodiment of the invention, a method of decompressing a compressed color image includes the following. The compressed color image includes at least an encoded frame for one color plane of the color image and prediction coefficients for the other two color plane frames of the color image. The one color plane frame of the color image is reconstructed from the encoded frame. The other two color plane frames of the color image are at least partially reconstructed from the reconstructed one color plane frame and the prediction coefficients.

Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.

Abstract: The present invention describes a structure for and a method of forming a first set and a second set of features in a substrate; covering the first and second set of features with a material; forming a third set of features in the material and removing the material to expose the first set of features, leaving the second set of features embedded below the material; measuring post-etch overlay between the first set and the third set of features; and measuring post-develop overlay between the second set and the third set of features.

Abstract: The present invention describes a structure for and a method of forming a first set and a second set of features in a substrate; covering the first and second set of features with a material; forming a third set of features in the material and removing the material to expose the first set of features, leaving the second set of features embedded below the material; measuring post-etch overlay between the first set and the third set of features; and measuring post-develop overlay between the second set and the third set of features.

Abstract: The present invention describes an aperture comprising an opaque plate with a central opening and at least one peripheral opening and a method for combining an on-axis component and at least one off-axis component of illumination light.

Abstract: The present invention discloses a method of increasing the contrast of an EUV mask at inspection by forming a multilayer mirror over a substrate; forming an absorber layer over the multilayer mirror; forming a top layer over the absorber layer; patterning the mask into a first region and a second region; and removing the top layer and the absorber layer in the first region.

Abstract: A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.