Abstract: A method of forming a silicon nitride-silicon dioxide, composite gate dielectric layer, offering reduced risk of boron penetration from an overlying boron doped polysilicon gate structure, has been developed. A porous, silicon rich silicon nitride layer is first deposited on a semiconductor substrate, allowing a subsequent thermal oxidation procedure to grow a thin silicon dioxide layer on the semiconductor substrate, underlying the porous, silicon rich silicon nitride layer. A two step anneal procedure is then employed with a first step performed in a nitrogen containing ambient to densify the porous, silicon rich silicon nitride layer, while a second step of the anneal procedure, performed in an inert ambient at a high temperature, reduces the foxed charge at the silicon dioxide-semiconductor interface.

Abstract: A substrate cassette having a conventional form, an open container having an upper entrance and a narrow lower opening formed by two side panels and two end panels. A preferred embodiment includes a train of substrate alignment channels on the inner surfaces of the two side panels, each channel is U shaped and having planar surface with a left surface, a right surface, and a bottom surface. An arcuate curbing member disposed on a left surface in each of the substrate alignment channels. The arcuate curbing member includes a top end with a thinner sloped profile facing the upper open entrance of the cassette allowing a substrate to slide through and under a stepped lower end.

Abstract: A current-perpendicular-to-plane (CPP) giant magnetoresistive (GMR) sensor of the synthetic spin valve type is provided, the sensor comprising a GMR stack having a substantially square lateral cross-section, a Cu spacer layer of smaller square cross-section formed centrally on the GMR stack and a capped ferromagnetic free layer of substantially square, but even smaller cross-sectional area, formed centrally on the spacer layer. The stepped, reduced area geometry of the sensor provides a significant improvement in its GMR ratio (DR/R), a reduced resistance, R, and elimination of Joule heating hot-spots in regions of high resistance such as the antiferromagnetic pinning layer and its seed layer.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.

Abstract: The present invention is generally directed to methods and systems for distributing image capture devices, images, and prints. One embodiment of the present invention advantageously provides cameras, such as digital cameras or film cameras, to consumers for free or at a discounted cost. In exchange, the consumer makes a commitment that a certain number of image reproduction or prints will be purchased by the consumer and/or by others. In another embodiment, a user receives prints with associated advertisements attached at a reduced price.

Abstract: A merged read/write magnetic recording head comprises a low magnetic moment first magnetic shield layer over a substrate. A read gap layer with a magnetoresistive head is formed over the first shield layer. A shared pole comprises a low magnetic moment second magnetic shield layer plated on a sputtered seed PLM layer over the read gap layer, a non-magnetic layer plated over the PLM layer and a HMM lower pole layer plated over the second magnetic shield layer. A write gap layer is formed over the first high magnetic moment pole layer of the shared pole. An upper pole comprises a high magnetic moment pole layer over the write gap layer.

Abstract: A method for tracking the MOS oxide thickness by the native threshold voltage of a “native” MOS transistor without channel implantation for the purpose of compensating MOS capacitance variations is achieved. The invention makes use of the fact that in MOS devices the threshold voltage is proportionally correlated to the oxide thickness of said MOS device. Said threshold voltage can therefore be used to build a reference voltage Vx+Vth which accurately tracks the MOS capacitance variations in integrated circuits. Circuits are achieved to create a frequency reference and a capacitance reference using said method. Additionally a method is introduced to create a capacitance reference in integrated circuits using said MOSFET capacitors.

Abstract: A nonvolatile memory device is achieved. The device comprises a string of MONOS cells connected drain to source. Each MONOS cell comprises a wordline gate overlying a channel region in a substrate. First and second control gates each overlying a channel region in the substrate. The wordline gate channel region is laterally between first and second control gate channel regions. An ONO layer is vertically between the control gates and the substrate. The nitride layer of the ONO layer forms a charge storage site for each control gate. First and second doped regions, forming a source and a drain, are in the substrate. The wordline gate channel region and the control gate channel regions are between the first doped region and the second doped region. First and second transistors connect the topmost MONOS cell to a first bit line and the bottom most MONOS cell to a second bit line.

Abstract: Electronic probe devices are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The ratio of the weight of the conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers to the weight of the base resin host is between about 0.20 and 0.40. The micron conductive powders are formed from non-metals, such as carbon, graphite, that may also be metallic plated, or the like, or from metals such as stainless steel, nickel, copper, silver, that may also be metallic plated, or the like, or from a combination of non-metal, plated, or in combination with, metal powders. The micron conductor fibers preferably are of nickel plated carbon fiber, stainless steel fiber, copper fiber, silver fiber, or the like.

Abstract: Low cost moldable antennas and methods of forming the antennas are described. Elements of the antennas are conductive loaded resin-based material having a conducting wire center. The conducting wire center can be single strand, multi-strand, insulated, or non-insulated wire. The conductive loaded resin-based material comprises micron conductor fibers, micron conductor powders, or in combination thereof homogenized within a base resin host wherein the ratio of the weight of the conductor fibers, conductor powders, or combination thereof to the weight of the base resin host is typically between about 0.20 and 0.40. The micron conductive fibers or powders can be stainless steel, nickel, copper, silver, carbon, graphite, or plated particles or fibers, or the like. The conducting metal wire can be copper, nickel, stainless steel, silver, or the like.

Abstract: Nano-oxide based current-perpendicular-to-plane (CPP) magnetoresistive (MR) sensor stacks are provided, together with methods for forming such stacks. Such stacks have increased resistance and enhanced magnetoresistive properties relative to CPP stacks made entirely of metallic layers. Said enhanced properties are provided by the insertion of magnetic nano-oxide layers between ferromagnetic layers and non-magnetic spacer layers, whereby said nano-oxide layers increase resistance and exhibit spin filtering properties. CPP sensor stacks of various types are provided, all having nano-oxide layers formed therein, including the spin-valve type and the synthetic antiferromagnetic pinned layer spin-valve type. Said stacks can also be formed upon each other to provide laminated stacks of different types.

Abstract: A method for tracking the MOS oxide thickness by the native threshold voltage of a “native” MOS transistor without channel implantation for the purpose of compensating MOS capacitance variations is achieved. The invention makes use of the fact that in MOS devices the threshold voltage is proportionally correlated to the oxide thickness of said MOS device. Said threshold voltage can therefore be used to build a reference voltage Vx+Vth which accurately tracks the MOS capacitance variations in integrated circuits. Circuits are achieved to create a frequency reference and a capacitance reference using said method Additionally a method is introduced to create a capacitance reference in integrated circuits using said MOSFET capacitors.

Abstract: An internal power system for a low power memory chip is described that provides a large capacity internal power source during chip power up and during an active state whereby memory operations are carried out. A memory chip standby state allows reduced chip power where the large capacity power source is turned off, and the memory chip internal voltages are provided by a small capacity power source. Switching between the standby and active states of the low power memory chip is accomplished by turning on and off a standby signal. The internal and external chip voltages are monitored during chip power up to insure that predetermined voltage levels have been reached before turning off the large capacity power source and placing the chip into a standby state.

Abstract: A double barrier resonant tunneling diode (RTD) is formed and integrated with a level of CMOS/BJT/SiGe devices and circuits through processes such as metal-to-metal thermocompressional bonding, anodic bonding, eutectic bonding, plasma bonding, silicon-to-silicon bonding, silicon dioxide bonding, silicon nitride bonding and polymer bonding or plasma bonding. The electrical connections are made using conducting interconnects aligned during the bonding process. The resulting circuitry has a three-dimensional architecture. The tunneling barrier layers of the RTD are formed of high-K dielectric materials such as SiO2, Si3N4, Al2O3, Y2O3, Ta2O5, TiO2, HfO2, Pr2O3, ZrO2, or their alloys and laminates, having higher band-gaps than the material forming the quantum well, which includes Si, Ge or SiGe. The inherently fast operational speed of the RTD, combined with the 3-D integrated architecture that reduces interconnect delays, will produce ultra-fast circuits with low noise characteristics.

Abstract: Capacitors are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The ratio of the weight of the conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers to the weight of the base resin host is between about 0.20 and 0.40. The micron conductive powders are formed from non-metals, such as carbon, graphite, that may also be metallic plated, or the like, or from metals such as stainless steel, nickel, copper, silver, that may also be metallic plated, or the like, or from a combination of non-metal, plated, or in combination with, metal powders. The micron conductor fibers preferably are of nickel plated carbon fiber, stainless steel fiber, copper fiber, silver fiber, or the like.

Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

Abstract: A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

Abstract: A method and circuit for verify and read of a nonvolatile memory cell without the use of a reference cell is described. The circuit comprises a sense amplifier that compares a voltage from the output of a read path of a selected bit line to a reference voltage. When the selected memory cell is erased, the bit line voltage is small pulling down the read path voltage below the reference voltage, which causes a sense amplifier output that is a logical “0”. When the selected cell has been programmed, the raise of the bit line voltage causes the bit line to be decoupled from the output of the read path. The read path output then continues to charge to a voltage higher than the reference voltage resulting in a logical “1” at the output of the sense amplifier.

Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.

Abstract: It has been found that the insertion of a copper laminate within CoFe, or a CoFe/NiFe composite, leads to higher values of CPP GMR and DRA. However, this type of structure exhibits very negative magnetostriction, in the range of high ?10?6 to ?10?5. This problem has been overcome by giving the copper laminates an oxygen exposure treatment When this is done, the free layer is found to have a very low positive magnetostriction constant. Additionally, the value of the magnetostriction constant can be adjusted by varying the thickness of the free layer and/or the position and number of the oxygen treated copper laminates.