Abstract: A system and method for constructing extensible markup language (XML) transactions comprising an XML format run on a computer system, wherein the method comprises pre-building static structures of an XML transaction, classifying dynamic structures of the XML transaction with empty tags and single occurrence classifiers for repeating dynamic structures, building a list of a sequence of the static and dynamic structures, linking the list to a type of XML transaction and a predetermined trading partner profile (TPP), and combining the static structures with the dynamic structures at a runtime of the XML transaction based on the sequence, the type of XML transaction, the TPP, and dynamic structures of the XML transaction, wherein the XML transaction occurs in a business-to-business (B2B) electronic environment.

Abstract: Disclosed are embodiments of a storage area network (SAN), a network interface card and a method of managing data transfers. These embodiments overcome the distance limitation of the Serial Attached Small Computer System Interface (SAS) physical layer so that SAS storage protocol may be used for communication between host systems and storage controllers. Host systems and storage controls are connected via an Ethernet interface (e.g., a legacy Ethernet or enhanced Ethernet for datacenter (EED) fabric). SAS storage protocol is layered over this Ethernet interface, providing commands and transport protocol for information exchange. Since the Ethernet interface has its own physical layer, the SAS physical layer is unnecessary and, thus, so is the SAS distance limitation. If legacy Ethernet is used, over-provisioning is used to avoid packet drops, or alternatively, TCP/IP is supported in order to recover from packet drops.

Abstract: A method for tuning performance of an operating system, the method comprising identifying all sources of operating system jitter; measuring the impact of each of the operating system jitter source; and tuning performance of the operating system, preferably by use of different approaches/techniques, which could include removing the sources of operating system jitter and/or delaying their execution and/or smoothening their execution over a longer period of time. Computer program code and systems are also provided.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: An energy storage apparatus has one or more camshafts, one or more cams connected to the camshaft, one or more followers contacting the cam, one or more biasing members connected to the follower, and one or more tracks connected to the follower. With embodiments herein the track limits movement of the follower to a constrained path intersecting the axis about which the camshaft rotates. Alternatively, the biasing member itself can limit the movement of the follower to this linear path. The biasing member can comprise any force member such as a spring, a piston, a flexible member, a compressible member, etc. that has the ability to bias the follower toward the axis of the camshaft. The embodiments herein store and transfer potential energy to reduce the total reflected torque on the motor.

Abstract: Analyzing transcripts of conversation between at least two users by receiving input information from a first user via a voice call, creating conversational transcripts from the information received from the first user, selecting at least one defined situation from a list of defined situations, identifying the selected situation in the conversational transcripts, identifying a set of procedural sequences by comparing the at least one identified situation in the conversational transcripts with knowledge derived from a corpus of historical conversational transcripts; and providing the set of procedural sequences to the first user.

Abstract: A structure includes two plates (planar plates) joined at right angles to one another. The first plate has a non-round opening (first opening) and can include tabs extending from one end (a first end) of the first plate. The second plate has a round opening and/or a notch, depending upon implementation. The second plate can also include tab openings on opposite sides of the round opening, again depending upon implementation. If a notch is used, the notch is positioned along an edge of the second plate (positioned along a second end of the second plate). When the first and second plates are connected, the optional tabs are positioned within the optional tab openings, a first end of the first plate being connected to the second end of the second plate. A locking structure is positioned within the first opening, the round opening, and the notch (if used). The locking structure connects the first plate to the second plate.

Abstract: Described are methods, apparatus and computer programs for determining run-time dependencies between logical components of a data processing environment. Components of the data processing environment are monitored by monitoring agents accessing run-time activity data via APIs of the managed system. A dependency generator identifies correlations between the run-time activity of the monitored components. For synchronous monitored systems, the dependency generator calculates an activity period for monitored components and determines which component's activity periods contain the activity periods of other components. Containment is used as an indicator of a likely dependency relationship, and a weighting is computed for each dependency relationship based on the consistency of containment.

Abstract: Methods and systems enhance a user's experience when working with documents and images. Such methods and systems, provide pictures, graphics, images, etc. related to words, phrases, sentences, etc. when a pointing device is hovered over the word or phrase to help the user to understand and remember the words, phrases, sentences, etc. being read, and/or increase the enjoyment of the user.

Abstract: Disclosed are a sound card and a method for limiting inputs to and outputs from that computer sound card. Specifically, the voltage of a feedback connection between the input and output of a sound card amplifier is increased from minimum voltage until an over-saturation condition occurs. This finds the “output voltage limit.” Thereafter, the output voltage of the amplifier is restricted to the output voltage limit. The feedback connection is then terminated and the voltage of the signal being supplied to the amplifier is increased from minimum voltage until the over-saturation condition again occurs. This finds the “input voltage limit.” Thereafter, the input supplied to the amplifier is restricted to the input voltage limit.

Abstract: Disclosed are embodiments of an integrated circuit device, method and design structure for selectively amplifying one of multiple received input signals. The embodiments incorporate at least two first stage transistors and a single second stage transistor. The first stage transistors are adapted to receive input signals from the same or different input signal sources and are each electrically coupled to the second stage transistor. A control circuit design is adapted to individually turn on a selected first stage transistor in conjunction with the second stage transistor, thereby activating a corresponding one of the cascode amplifiers and allowing the input signal received by the selected first stage transistor to be separately amplified.

Abstract: Disclosed is a sheet buffering and inverting device having a sheet transport path and multiple sheet inverter paths extending upward and/or downward there from. Sheets being transported through the sheet transport path are selectively diverted into the sheet inverter paths, held, and subsequently fed back into the sheet transport path such that they are inverted. Optionally, an additional sheet transport path can branch off the sheet transport path upstream of the sheet inverter paths and can connect to the distal end of each of the sheet inverter paths to allow sheets to be buffered without being inverted. This device can be incorporated into a discrete module of a modular printing system to ensure sheets are properly merged and oriented after processing by multiple printing engines. Alternatively, it can be incorporated into a standalone printing system to ensure sheets are properly buffered and/or inverted prior to processing by a single printing engine.

Abstract: Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.

Abstract: A method for producing a configurable content-addressable memory (CAM) cell design, in which the method includes: inputting the configurable CAM cell design to a computer, the configurable CAM cell design capable of being configured as one of a binary CAM design and a ternary CAM design, depending on connections of a metal overlay; selecting one of a first metal overlay design for the binary CAM design and a second metal overlay design for a ternary CAM design; if the first metal overlay design is selected, then combining the first metal overlay design with the configurable CAM cell design to produce a binary CAM design including two binary CAM cells with a single search port, and outputting the binary CAM design; and if the second metal overlay design is selected, then combining the second metal overly design with the configurable CAM cell design to produce a ternary CAM design including a single ternary CAM cell with two search ports, and outputting the ternary CAM design by the computer.

Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed.

Abstract: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: A method of associating a given text document with relevant structured data is disclosed. The method receives as inputs a text document, and structured data in the form of a relational database. The method then identifies terms in the text document, and searches and queries the structured data using the terms to identify fragments of the structured data that are relevant to the document. Finally, the text document and the identified fragments of structured data are output to a user.

Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.