Patents Represented by Attorney H. C. Chan
  • Patent number: 6690202
    Abstract: In some communications circuits a phenomenon called duty-cycle distortion—that is, a distortion of the apparent duration of the pulses in clock signals—causes the circuits to read clock signals as having a different duration than intended. Accordingly, the inventors devised unique circuitry for correcting or preventing this distortion. One exemplary circuit uses a voltage divider, comprising a pair of transistors, to set the DC or average voltage of the clock signals input to the digital circuit at a level approximating the logic threshold voltage of the digital circuit. In another example, a feedback circuit drives the DC or average voltage of signals input to the digital circuit to match a reference voltage that is substantially equal to the logic threshold voltage. In both examples, equating the DC or average voltage of the clock signals to the logic threshold voltage of the digital circuit reduces or prevents duty-cycle distortion.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: February 10, 2004
    Assignee: Xilinx, Inc.
    Inventors: Eric Douglas Groen, Charles Walter Boecker
  • Patent number: 6684271
    Abstract: The present invention allows preloading of channel context in advance of actual channel change in a digital communication system. The system uses a channel identification signal to identify the present channel number of data on a data bus. Before the actual change in channel, a future channel number is inserted into the channel identification signal. Another signal is used to indicate the location of the future channel number in the channel identification signal. As a result, the system is able to know in advance the new channel number. The corresponding context can be loaded before the arrival of the new channel data.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: January 27, 2004
    Assignee: Xilinx, Inc.
    Inventor: Kent Blair Dahlgren
  • Patent number: 6675310
    Abstract: A computer implemented apparatus and method that automates the entry, modification, analysis, and generation of test benches from electrical circuits, both of which are specified as hardware description language (HDL) files. The computer implemented-method and apparatus also provides a unique mechanism that blends entry and display of timing requirements that must be met by the electric circuit.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: January 6, 2004
    Assignee: Xilinx, Inc.
    Inventors: Andrew Maurice Bloom, Rodrigo Jose Escoto
  • Patent number: 6664808
    Abstract: FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: December 16, 2003
    Assignee: Xilinx, Inc.
    Inventors: Zhi-Min Ling, Jae Cho, Robert W. Wells, Clay S. Johnson, Shelly G. Davis
  • Patent number: 6662285
    Abstract: A data processing system having a user configurable memory controller, one or more local block RAMs, one or more global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: December 9, 2003
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Douglass, Prasad L. Sastry, Mehul R. Vashi, Robert Yin
  • Patent number: 6642788
    Abstract: A differential amplifier amplifies input signals and includes first and second differential input transistor pairs. The first input pair controls output voltages by adjusting sink currents coupled to the outputs. The second pair of transistors compliments the first pair by dynamically adjusting a current sourced to the outputs. A common mode circuit has also been described that adjusts both the current sourced to the outputs and the sink currents. In one embodiment, the amplifier is fully differential and controls both current source transistors and current sink transistors coupled to the amplifiers outputs.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: November 4, 2003
    Assignee: Xilinx, Inc.
    Inventor: Firas N. Abughazaleh
  • Patent number: 6624668
    Abstract: Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: September 23, 2003
    Assignee: Xilinx, Inc.
    Inventors: Moises E. Robinson, Michael J. Gaboury, Bernard L. Grung
  • Patent number: 6621307
    Abstract: A method and circuit for determining variation between an input clock signal (CLK0) and a reference clock signal (REFCLK) is provided. A plurality of time shifted input clock signals (CLK0, CLK1, . . . , CLK09) can be generated from a single input clock signal (CLK0). The plurality of time shifted input clock signals (CLK0, CLK1, . . . , CLK09) can be sampled at successive periodic intervals occurring relative to the reference clock signal (REFCLK). For each of the time shifted input clock signals (CLK0, CLK1, . . . , CLK09), a sampled value for a succeeding and a preceding periodic interval can be compared to determine whether there is a variation between an input clock signal (CLK0) and a reference clock signal (REFCLK).
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: September 16, 2003
    Assignee: Xilinx, Inc.
    Inventors: Ahmed Younis, Michael A. Nix
  • Patent number: 6617877
    Abstract: A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: September 9, 2003
    Assignee: Xilinx, Inc.
    Inventors: Warren E. Cory, Hare K. Verma, Atul V. Ghia, Paul T. Sasaki, Suresh M. Menon
  • Patent number: 6617887
    Abstract: A differential comparator having offset correction and common mode control for providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset tolerance, as well as fast decision time.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: September 9, 2003
    Assignee: Xilinx, Inc.
    Inventor: Michael A. Nix
  • Patent number: 6617984
    Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: September 9, 2003
    Assignee: Xilinx, Inc.
    Inventors: Joseph Neil Kryzak, Thomas E. Rock
  • Patent number: 6601227
    Abstract: Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is reserved on the ASIC substrate for fabricating the buffers, which are selectively connected by local metal and diffusion structures to form long distance interconnections. Signals are passed from an ASIC circuit structure to a selected long distance interconnection by connecting an output terminal of the ASIC structure either to the input terminal of a buffer located at one end of the interconnection, or by connecting the output terminal directed to a line segment of the interconnection.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: July 29, 2003
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 6594610
    Abstract: A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: July 15, 2003
    Assignee: Xilinx, Inc.
    Inventors: Shahin Toutounchi, Anthony P. Calderone, Zhi-Min Ling, Robert D. Patrie, Eric J. Thorne, Robert W. Wells
  • Patent number: 6586964
    Abstract: A system for calibrating an adjustable termination resistor for a low voltage differential signaling (LVDS) system is provided. The system includes an adjustable termination resistor located on a chip and a reference termination resistor located off the chip. A bias circuit coupled to the adjustable termination resistor and the reference termination resistor causes the same current to flow through the adjustable termination resistor and the reference termination resistor. A comparator is configured to compare a first voltage drop across the adjustable termination resistor and a second voltage drop across the reference termination resistor. A control circuit is coupled to receive an output signal from the comparator. If the output signal indicates that the adjustable termination resistor has a desirable value with respect to the reference termination resistor, then the control circuit stops the calibration operation.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: July 1, 2003
    Assignee: Xilinx, Inc.
    Inventors: Michael Kent, Michael A. Nix
  • Patent number: 6566950
    Abstract: A high-speed, low distortion line driver that includes an amplifying circuit and a differential input amplifier. The differential input amplifier includes a 1st amplifying transistor, a 2nd amplifying transistor, a 1st controlled current source, and a 2nd controlled current source. The 1st amplifying transistor is coupled in series with the 1st controlled current source and the 2nd amplifying transistor is coupled in series with the 2nd controlled current source. The 1st and 2nd amplifying transistors are operably coupled to receive a differential input signal and provide a gained and level shifted representation of the differential input signal based on the controlled currents provided by the 1st and 2nd current sources. The amount of gain is based on the transconductance properties of the 1st and 2nd amplifying transistors and of the 1st and 2nd current sources.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: May 20, 2003
    Assignee: Xilinx, Inc.
    Inventor: Shahriar Rokhsaz
  • Patent number: 6564254
    Abstract: When a user selects an arbitrary symbol 75 (word, phrase, sentence, graphic, image, etc.) from an arbitrary application 3 on a client computer 3, and copies this symbol 75 to a clipboard 79, a linker 23, being a terminate-and-stay-resident-type process, automatically captures that symbol 81 from the clipboard 79. Similarly, when a user types at a keyboard from an arbitrary application 207, those typed characters are first passed to an input method editor 201, where they are temporarily stored within a buffer 211, and when the user enters a prescribed “okay” key sequence the characters within that buffer 211 are converted as necessary and passed to the application 207, but if the user enters a prescribed “link” key sequence, a character string determining component 213 of the input method editor 201 passes the characters within the buffer 211 to a linker 209. In either case, the linker 23 sends the captured symbol to a URL server 5.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: May 13, 2003
    Assignee: Dream Technologies Corporation
    Inventors: Wataru Shoji, Daisuke Tabuchi, Ichiro Nakajima, Gabriele Gramlich
  • Patent number: 6535030
    Abstract: A differential comparator having offset correction and common mode control providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset tolerance, as well as fast decision time.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: March 18, 2003
    Assignee: Xilinx, Inc.
    Inventor: Michael A. Nix
  • Patent number: 6522167
    Abstract: A data processing system having a user configurable memory controller, one or more block RAMS, and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.
    Type: Grant
    Filed: January 9, 2001
    Date of Patent: February 18, 2003
    Assignee: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Stephen M. Douglass, Mehul R. Vashi, Steven P. Young
  • Patent number: 6518893
    Abstract: A method and apparatus for multilevel signaling includes processing that begins by determining multilevel signaling operation conditions. The processing then continues by generating an adjust signal based on the determined multilevel signaling operation conditions. The adjust signal is used to change the magnitude of the multilevel signals produced via the multilevel encoding. The adjust signal may vary a supply voltage and/or vary gain of an amplifier stage.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: February 11, 2003
    Assignee: Xilinx, Inc.
    Inventor: Moises E. Robinson
  • Patent number: 6507296
    Abstract: A current source calibration circuit and methodology reduce noise generated by current switching. In one embodiment, the calibration circuit provides a random or pseudo-random clock signal to control a switching of calibration circuit. A clock signal generator has been described that provide a number of clock signals having different phases. In one embodiment, the clock signals are used to select a current source of a DAC for calibration. By using a random clock to select the current source, noise, which is generated by switching a primary current source with a backup current source, is spread out over a wider frequency range.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: January 14, 2003
    Assignee: Xilinx, Inc.
    Inventors: Yvette P. Lee, Marwan N. Hassoun