Patents Represented by Law Firm Haverstock & Associates
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Patent number: 5517556Abstract: An improved telephone call processing apparatus for processing facsimile messages. The facsimile processing apparatus comprises a message control system including a voice control unit (VCU), a control processor unit (CPU), and a telephone line card. Multiple buses including a high speed voice/data bus, a control bus, and a time division multiplexed (TDM) bus are used to couple the VCU, the CPU and the line card. The high speed data bus is dedicated for voice and data transmission only. The control bus is dedicated to command controls and system background tasks. The TDM bus is used to make full duplex voice connections between individual line card ports and facsimile message controller modem channels. The CPU manages the connections between line card ports and fax channels. The VCU comprises a high speed processor and a control processor.Type: GrantFiled: September 18, 1992Date of Patent: May 14, 1996Assignee: VMX, Inc.Inventors: Gregory E. Pounds, David J. Ladd, Tim J. Kusumi, Robert H. Sinn, Eric K. Wood
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Patent number: 5515310Abstract: A content addressable memory cell includes six transistors connected together to perform memory read, memory write, and matching operations. This cell has the ability to perform typical memory write and memory read operations as well as the capability of signalling whether or not its stored data matches data that is being searched for. A cross-coupling scheme is used in the memory cell so that a high potential will always be stored on the gate of a transistor whose source is at ground. This cross-coupling scheme increases the amount of charge stored on the storage transistor and decreases the required frequency of refresh operations. In addition to the transistors configured to store data, an additional transistor configured as a diode is used as a rapid discharge path to maximize the efficiency of the cell during a read operation. During a match operation another transistor is utilized to discharge the Match line quickly in the event the stored data does not match the data that is being searched for.Type: GrantFiled: December 14, 1994Date of Patent: May 7, 1996Assignee: Advanced Hardware Architectures, Inc.Inventor: Kel D. Winters
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Patent number: 5510727Abstract: The invention employs an active element, a p-channel MOSFET, between a regulated voltage and a SCSI terminating line. An "ideal" current source terminator is most effective when a signal line is negated (low-to-high transition), whereas a resistive terminator is most effective when a signal line is asserted (high-to-low transition). The I-V characteristics of a p-channel MOSFET, wherein the relationship between the termination voltage and the termination current is characterized by a nonlinear and smooth voltage versus current curve, provide an optimized transient response for signal negations and signal assertions on a SCSI bus.Type: GrantFiled: June 27, 1994Date of Patent: April 23, 1996Assignee: Micro Linear CorporationInventors: Daniel D. Culmer, Mark R. Vitunic
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Patent number: 5502696Abstract: A subcode R-W channel data de-interleaving and de-scrambling method and apparatus includes the ability to de-interleave and de-scramble the encoded subchannel data without the necessity of storage elements, by dynamically calculating the final location of each byte of data within a packet as it is read from the CD-Rom. A pack counter monitors the pack number of the current byte of data. An index counter monitors the location of the current data within a pack. A subtractor uses the values from the pack counter and the index counter to obtain an input value, a first portion of which is supplied to a first offset generator. A second portion of the subtractor output is used to select a base address. The first offset generator determines the pack number of the current byte of data after the de-interleave process. A second offset generator receives a value from the index counter and generates a corresponding value.Type: GrantFiled: September 23, 1994Date of Patent: March 26, 1996Assignee: Cirrus Logic, Inc.Inventors: Tony J. Yoon, Michael J. McGrath, Phuc Tran
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Flash memory mass storage architecture incorporating wear leveling technique without using cam cells
Patent number: 5485595Abstract: A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit and method are provided for evenly using all blocks in the mass storage. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old versions of a block, a count to determine the number of times a block has been erased and written and an erase inhibit flag. Reading is performed by providing the logical block address to the memory storage. The system sequentially compares the stored logical block addresses until it finds a match.Type: GrantFiled: October 4, 1993Date of Patent: January 16, 1996Assignee: Cirrus Logic, Inc.Inventors: Mahmud Assar, Petro Estakhri, Siamack Nemazie, Mahmood Mozaffari -
Patent number: 5481468Abstract: In data logging applications, a method and apparatus are disclosed for storing an increasing number of consecutive real-time data points, such as those descriptive of AC (alternating current) power line parameters, in a fixed amount of memory by periodically applying a novel compression technique. The compression technique preserves time relationships in the data while maximizing the level of detail consistent with a limited amount of memory. When the memory is full each data point stored is paired with another data point and one value is calculated that will represent the pair of data points, reducing the necessary memory to half and allowing more data points to be stored.Type: GrantFiled: August 4, 1992Date of Patent: January 2, 1996Assignee: Basic Measuring Instruments, Inc.Inventor: Alexander McEachern
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Patent number: 5479638Abstract: A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoids an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit for evenly using all blocks in the mass storage is provided. These advantages are achieved through the use of several flags, a map to directly correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old version of a block, a count to determine the number of times a block has been erased and written and erase inhibit.Type: GrantFiled: March 26, 1993Date of Patent: December 26, 1995Assignee: Cirrus Logic, Inc.Inventors: Mahmud Assar, Siamack Nemazie, Petro Estakhri
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Patent number: 5479368Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed.Type: GrantFiled: September 30, 1993Date of Patent: December 26, 1995Assignee: Cirrus Logic, Inc.Inventor: Parviz Keshtbod
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Patent number: 5476801Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed.Type: GrantFiled: February 3, 1995Date of Patent: December 19, 1995Assignee: Cirrus Logic, Inc.Inventor: Parviz Keshtbod
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Patent number: 5471401Abstract: An apparatus and method for characterizing an alternating current power line which uses a library of waveforms and associated spectra of digitally sampled alternating current power system voltage or current waveforms. The library of waveforms is built as new waveforms are measured from the alternating current power line. A measured waveform that is not found in the library will be converted to frequency-domain representation, using a Discrete Fourier Transform, that will then be stored in the library. When the library becomes full, the frequency domain representation of the new waveform will be stored in place of the least used waveform currently stored in the library.Type: GrantFiled: September 9, 1992Date of Patent: November 28, 1995Assignee: Basic Measuring Instruments, Inc.Inventors: Jamie Nicholson, Alexander McEachern
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Patent number: 5467620Abstract: A U-lock includes a detachable header with extensions that fit around the arms of the U-bar and extend along the length of those arms to provide strength to the U-lock. The header can be used so that its base is locked at the end of the arms of the U-shaped bar or it can be inverted when locking smaller objects so that its base is locked along the lengths of the arms taking up some of the gap between the locked object and the base of the header. The header is locked to the arms of the U-shaped bar by a locking mechanism which secures the header to the arms of the U-shaped bar in four different places, two on each arm. The U-lock and header with extensions can also be used in combination with security spacers for further security.Type: GrantFiled: April 7, 1994Date of Patent: November 21, 1995Inventor: Richard H. Byrd, Jr.
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Patent number: 5467042Abstract: A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits.Type: GrantFiled: November 8, 1993Date of Patent: November 14, 1995Assignee: Cirrus Logic, Inc.Inventors: Stephen A. Smith, Bryan Richter, Dave M. Singhal
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Patent number: 5454492Abstract: A decorative cover is provided which easily fits over a water bottle mounted on a water dispenser. This cover provides a variably changeable decor that can fit different tastes and environments. Further, this cover includes accessory features such as a handle for easy removal of the cover, a cup dispenser, and a pouch for storing water delivery schedules, bills and the like. In one embodiment the cover is constructed of a loose fitting material and includes a top portion and a side portion. In an alternate embodiment the cover is constructed of a rigid material designed to stand on its own around the water bottle. In this embodiment the cover can include a top portion or can leave the water bottle exposed on the top. This rigid material can be foam rubber coated with plastic for writing and erasing messages or metallic for attaching messages by magnetic means.Type: GrantFiled: March 22, 1994Date of Patent: October 3, 1995Inventors: Lionel Hunter, Byron Cobb
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Patent number: D363453Type: GrantFiled: December 9, 1993Date of Patent: October 24, 1995Assignee: Cash -Clip GmbHInventor: Bruno Herdt
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Patent number: D370257Type: GrantFiled: January 9, 1995Date of Patent: May 28, 1996Inventor: Warren S. Christopher