Patents Represented by Attorney, Agent or Law Firm Haynes and Boone LLP
  • Patent number: 8336002
    Abstract: An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gwan Sin Chang, Yi-Kan Cheng, Ivy Chiu, Ke-Ying Su
  • Patent number: 8334197
    Abstract: The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Da-Yuan Lee, Kuang-Yuan Hsu, Xiong-Fei Yu, Wei-Yang Lee, Matt Yeh
  • Patent number: 8332669
    Abstract: A port securing module includes a power gate that is operable to be coupled in series to a power source and to a load. A resistor is coupled in parallel to the power gate. An operational amplifier includes an inverting input and a non-inverting input that couple the operational amplifier in parallel to each of the power gate and the resistor. The operational amplifier also includes an output that is operable to indicate whether a load is coupled to the power gate and, if a load is coupled to the power gate, supply a voltage to activate the power gate such that power is supplied to the load.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: December 11, 2012
    Assignee: Dell Products L.P.
    Inventors: Ardian Darmawan, Curtis Ray Genz, Clay Phennicie
  • Patent number: 8331352
    Abstract: A method for interworking supplementary call services between different VOIP protocols is provided. The method comprises receiving, during a call between a first end device and a second end device, a first message in a first protocol format for the second end device to transfer the call to a third end device; determining interworking information to interwork the first message to a second message in a second protocol format; generating the second message based on the interworking information, such that the second message initiates the call transfer to the third end device.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: December 11, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Parameswaran Kumarasamy, Paul R. P. Chu, Jayesh Chokshi, Sunila R. Ainapure, Sandeep Singh Kohli, Sabita Jasty, Vijay Kannan
  • Patent number: 8329484
    Abstract: The present disclosure provides an illuminating system including a light emitting device and a luminescent material disposed approximate the light-emitting device. The luminescent material includes a strontium silicon nitride (SrSi6N8) doped by one of cerium (Ce3+) and cerium (Ce3+) and lithium (Li+).
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: December 11, 2012
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chiao-Wen Yeh, Ru-Shi Liu
  • Patent number: 8330227
    Abstract: A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng Chiang Hung, Huai-Ying Huang, Ping-Wei Wang
  • Patent number: 8330559
    Abstract: A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chung-Hsien Lin, Chia-Hua Chu
  • Patent number: 8332473
    Abstract: A system and method for managing multiple message format communication that may provide the ability to route, transform, and augment inbound messages, so that virtually any outbound message may be constructed.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: December 11, 2012
    Assignee: American Airlines, Inc.
    Inventors: Monty Fouts, Richard Bowman, Mark Hanson
  • Patent number: 8329546
    Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Da-Yuan Lee, Kuang-Yuan Hsu, Matt Yeh, Yi-Chen Huang, Fan-Yi Hsu, Hui Ouyang, Ming-Jie Huang, Shin Hsien Liao
  • Patent number: 8329521
    Abstract: A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company. Ltd.
    Inventors: Harry Hak-Lay Chuang, Bao-Ru Young, Sheng-Chen Chung, Kai-Shyang You, Jin-Aun Ng, Wei Cheng Wu, Ming Zhu
  • Patent number: 8328993
    Abstract: Proposed is a pyrolysis reactor for processing solid municipal and domestic wastes by means of a pyrolytic reaction in the pyrolysis chamber without access of oxygen to the reaction system. The reactor is characterized by containing two waste-feeding screws which have tapered shapes, a gap between the outer surfaces of the threads, are inclined in the vertical plane and converge towards each other in a horizontal plane in the direction from the inlet to the outlet end. The gap is adjustable with diminishing toward the outlet end.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: December 11, 2012
    Assignee: Greenlight Energy Solutions, LLC
    Inventors: Arkady Feerer, Marat Hasbulatovich Kulakov, Denis Zagorsky
  • Patent number: 8332311
    Abstract: A system, according to one embodiment, includes a hybrid account provided by an issuer to a user, the hybrid account having a balance, the balance being either positive, zero, or negative; and a financial instrument including a hybrid card, the hybrid card providing access to the hybrid account, in which transactions using the hybrid card provide interchange income to the issuer, the issuer charges interest to the hybrid account when the balance is negative, and the issuer pays interest to the hybrid account when the balance is positive.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: December 11, 2012
    Assignee: eBay Inc.
    Inventor: Edward Kim
  • Patent number: 8329360
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Patent number: 8332314
    Abstract: A system and method enables trusted sources to easily approve requests for money transfers by simply typing in a yes or equivalent.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: December 11, 2012
    Inventor: Kent Griffin
  • Patent number: 8332797
    Abstract: The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Chou Cheng, Tsong-Hua Ou, Wen-Hao Liu, Ru-Gun Liu, Wen-Chun Huang
  • Patent number: 8328805
    Abstract: The present invention provides a technique for percutaneous intramedullary fixation. A protective outer sheath is provided for internal fixation of the proximal tibia. Additionally, a unique intramedullary plate is provided that is adapted for percutaneous insertion into the intramedullary canal of a long bone. A plate holder is also provided that may be utilized through the outer sheath to drive and position a fixation plate within the intramedullary canal.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: December 11, 2012
    Inventor: J. Dean Cole
  • Patent number: 8327165
    Abstract: A power supply input circuit includes an input node configured to removeably couple to an electrical source. A solid state switch is coupled between the input node and a capacitive load. An RC soft start circuit is coupled to the input node and the switch. The soft start circuit has a capacitor that causes the switch to increasingly pass electrical power from the source to the load as the capacitor charges from the source. An active reset circuit is coupled to the soft start circuit. The reset circuit is configured to detect when the source is removed from the input node and in response to the source being removed from the input node, the reset circuit discharges the capacitor to reset the soft start circuit.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 4, 2012
    Assignee: Dell Products L.P.
    Inventors: Joseph Alexander Clegg, Mohammed K. Hijazi, Merle J. Wood, III
  • Patent number: 8323870
    Abstract: The present disclosure provides a resist utilized in a photolithography patterning process. The resist includes a polymeric material having a plurality of zipper molecules, each including a first zipper portion and a second zipper portion, wherein the first and second zipper portions each include a plurality of zipper branches bonded together in pairs and cleavable to one of thermal energy, radiation energy, and chemical reaction.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fong-Cheng Lee, Ching-Yu Chang
  • Patent number: 8324002
    Abstract: Provided is a method of forming and/or using a backside-illuminated sensor including a semiconductor substrate having a front surface and a back surface. A transfer transistor and a photodetector are formed on the front surface. The gate of the transfer transistor includes an optically reflective layer. The gate of the transfer transistor, including the optically reflective layer, overlies the photodetector. Radiation incident the back surface and tratversing the photodetector may be reflected by the optically reflective layer. The reflected radiation may be sensed by the photodetector.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Hsu, Dun-Nian Yaung, Ching-Chun Wang
  • Patent number: D672880
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: December 18, 2012
    Assignee: SPD Swiss Precision Diagnostics GmbH
    Inventors: Paul Laverack, Richard Luxton