Abstract: The negative supply voltage used by the drivers during sector or chip level erase operations is decoded separately from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, and a set of wordline drivers. The wordline drivers are coupled to the first and second supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors.

Abstract: A method for determining successful programming of a set of memory cells in an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array, word lines coupled with corresponding rows of cells in the array, and bit latches coupled to the respective bit lines. The method includes applying a word line voltage to a word line across which memory cells in the set of memory cells are accessible. A potential applied to memory cells in the set of memory cells is raised. A current load is caused from the bit line. Changes in respective voltage levels of bit lines in the set of bit lines are responded to in parallel to store a constant in bit latches in the set of bit latches coupled to bit lines on which the respective voltage levels pass a determinate threshold during the step of applying a word line voltage. An integrated circuit memory is described.

Abstract: A device for coupling a first network medium to a second network medium. A first port is coupled to the first network medium and a second port coupled to the second network medium. A memory stores a first plurality of indications and a second plurality of indications. The indications in the first plurality of indications correspond to respective sets of addresses and indicate whether at least one address in the respective set of addresses may be accessible through the first network medium. The indications in the second plurality of indications correspond to respective sets of addresses and indicate whether at least one address in the respective set of addresses may accessible through the second network medium. A connecting circuit is coupled to the first port, the second port, and the memory. The connecting circuit causes the ports to pass or block a packet from the first network to the second network. The packet has a destination address.

Abstract: A new flash memory cell structure and operational bias approach for allowing programming operations significantly faster than prior approaches, is based on the use of band-to-band tunneling induced hot electron injection in cells to be programmed and on the use of triple-well floating gate memory structures. The method comprises inducing band-to-band tunneling current from the semiconductor body to one of the source and drain near the channel, and applying a positive bias voltage to the control gate to induce hot electron injection into the floating gate. The other of the source and drain terminals is floated, that is disconnected so that current does not flow through that terminal. The band-to-band tunneling current is induced by applying a reference potential to one of the source and drain sufficient to establish conditions for the band-to-band tunneling current.

Abstract: A process for spreading and flowing in a flowable dielectric during manufacture of an integrated circuit resulting in greater planarity and better gap filling ability. The process involves spinning the integrated circuit while controlling evaporation of the solvent from the flowable dielectric to increase the amount of flow in time and decrease spin velocity during flow in to improve planarity in gap filling ability. The process includes supporting the integrated circuit in a chamber; dispensing the flowable dielectric in a solvent on the integrated circuit in the chamber; covering the integrated circuit to provide a controllable environment within the chamber after the step of dispensing; spinning the integrated circuit while controlling the controllable environment to spread and flow in the flowable dielectric; uncovering the integrated circuit within the chamber; spinning the integrated circuit to spin off flowable dielectric; and curing the flowable the flowable dielectric.

Abstract: A technique for storing multiple bits per cell in a read only memory device, provides for two kinds of code implants in the memory array. A shallow implant such as used in prior art mask ROMs is used for coding a first bit, and a deeper implant is used for coding a second bit in the memory cells. Furthermore, the cells are implemented in a semiconductor substrate so that the channels of the transistors in the mask ROM can be biased. The memory cells include as isolation layer formed in the semiconductor substrate, and a channel well formed in the isolation layer. The device includes resources to apply a first bias potential such as ground, to channel regions of memory cells in the array. When the first bias potential is applied through the channel regions, the memory cells have particular thresholds determined at least in part by the dope concentrations in the channel regions. The device also includes resources to apply a second bias potential to the channel regions of the memory cells.

Abstract: An on chip voltage generation circuit suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts) includes a sense circuit on the integrated circuit which generates an output indicating a level of the supply voltage. The on chip voltage supply circuit generates the on chip voltage in response to the output of the sense circuit and the supply voltage. The sense circuit output indicates the level of the supply voltage so that the on chip voltage supply circuit is able to adapt the amount of boosting utilized to produce the on chip voltage in response. The on chip voltage supply circuit generates the word line voltage at a node coupled to word line driving circuits in the device.

Abstract: A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows Fowler Nordheim (F-N) tunneling with lower absolute value bias potentials. Thus, the floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area.

Abstract: A recovery circuit for recovering the control gate and the channel well of a floating gate memory cell to a first recovery potential and a second recovery potential respectively after a program or erase process has been performed on the cell is provided. The floating gate memory cell may include the control gate coupled to a first node at a first program/erase potential, a floating gate, the channel well coupled to a second node at a second program/erase potential having a first conductivity type, and drain and source regions within the channel well having a second conductivity type different from the first. The recovery circuit includes control circuitry that provides a recovery control signal indicating when the program or erase process has been completed, and a coupling circuit that connects the control gate to the channel well in response to the recovery control signal.

Abstract: In a floating gate memory that has a buffer that can be coupled to a set of floating gate memory cells in the memory, a method of writing to a selected portion of the set of floating gate cells. For example, a method of writing a byte to a floating gate memory where the memory uses a page buffer reads and writes to an entire row of cells at a time. Store contents of the set of floating gate cells into the buffer, store the data into a portion of the buffer corresponding to the selected portion of the set of floating gate cells, and store contents of the buffer into the set of floating gate cells. An improved floating gate memory is disclosed in which data may be loaded into a portion of the floating gate cells in a set of cells that may be coupled to a buffer.

Abstract: A pulsed RF oscillator employing a BIAS-ON path and a QUENCH path to produce fast turn-on and fast turn-off RF bursts with well-controlled burst width. The oscillator further includes amplitude and stability control elements, and a 5.8 GHz microstrip implementation is disclosed. The pulsed RF oscillator can be configured with quadrature RF homodyne detectors to form a range-gated pulse-Doppler motion sensor system for sensing target motion within a gated region. The sensor includes a transmitter for transmitting a sequence of RF bursts comprised of a number of cycles at the transmitter frequency. The sensor further includes a receiver responsive to the transmitted bursts and burst echoes from moving targets within its sensing field. The receiver produces Doppler signal with an amplitude representative sum of the transmitted burst and the echo burst. A Doppler motion response occurs for moving targets within a region sharply defined by the transmitted burst width.

Abstract: Systems and methods are described for providing low-voltage triggering electrostatic discharge (ESD) protection in the context of integrated circuits. A low-voltage triggering electrostatic discharge protection circuit has a low trigger voltage and can turn on quickly to provide a low resistance path. The protection circuit can be employed in power bus, input, and input/output pin ESD protection configurations. This protection circuit is compatible with complementary metal oxide semiconductor (CMOS) processes. High ESD performance can even be achieved with devices fabricated in accordance with advanced CMOS processes.

Abstract: A system and method for assembling or generating content addressable video based on storing a plurality of frames of video data at addressable storage locations. Each frame of video data is stored with a tag which indicates the contents of the video image defined by the associated frame. For assembly, a processing unit assembles a content video image in response to the tags; the content video image, including positions for corresponding frames of video data. Finally, a means, such as a look up table, is provided for associating the positions in the content video image with addresses of storage location storing the corresponding frames of video data. A user input device is provided by which the user selects a particular frame of video data, by selecting a position in the content video image, such as by positioning a cursor on the selected position.For generating content addressable video, the content video image is first generated.

Abstract: The negative supply voltage and isolation well bias used by the drivers during sector or chip level erase operations are decoded separately from each other and from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry using shared isolation well MOS transistors coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, a third supply voltage source for the shared isolation well and a set of wordline drivers.

Abstract: A pulse Doppler radar motion sensor system and method for sensing target motion within a gated region is provided with approximately constant response versus target distance. The sensor includes a transmitter for transmitting a sequence of RF bursts comprised of a number of cycles at the transmitter frequency. The transmitted burst width alternates at a pattern frequency to provide a pattern of varying burst widths. The sensor includes a receiver responsive to the transmitted bursts and burst echoes from moving targets within its sensing field. The receiver produces a pattern frequency with a signal amplitude representative of the difference in moving target response for two different range gated regions defined by the transmitted burst widths. This difference is detected to provide a range invariant target motion response in a sharply defined region. Another mode provides a quadrature receive channel for target direction determination.

Abstract: A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area.

Abstract: A memory cell having an asymmetric source and drain connection to buried bit-lines providing a Fowler-Nordheim tunneling region and a non-tunneling region defined by a bird's beak encroachment on each of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single bit-line.

Abstract: Methods and systems for floating gate memory cell array erasure with wordline level retry are disclosed. A data storage device includes a memory array organized into a plurality of blocks of memory cells, each of the blocks including a plurality of wordlines of memory cells. An energizing circuit applies energizing voltages to the memory cells to read and program addressed cells, and to erase selected blocks of memory cells, or the whole memory array. An erase verify circuit separately verifies erasure of the individual wordlines that compose each block that is erased. The control logic can include a plurality of shared wordline erase flags which correspond to respective wordlines in each particular block as they are verified. If the wordline passes erase verify, then the wordline erase flag is reset. Only those wordlines having a set wordline erase flag after the erase verify operation are re-erased.

Abstract: A non-volatile memory device based on an array of floating gate memory cells includes read, erase, program and verify control logic for the array. A status register is coupled with the control logic and stores statistics determined during verify operations concerning at least one of the erase and program operations. For instance, the control logic may include erase verify resources and program verify resources, and the statistics will indicate a number of memory cells which fail erase or program verify. Alternatively, the statistics may indicate whether a threshold number of sequential bytes in the memory fail program verify for a program or erase operation involving a page or sector of data. In addition, defective addresses can be stored. With the status register, the number of program and erase retries for the device can be significantly reduced, allowing application of the device to real time storage systems. Many real time storage problems are fault tolerant.

Abstract: An embodiment of the invention provides a buffer circuit having reduced power consumption. The buffer circuit comprises a power saving switch coupled to a buffer at a bias node. The buffer has an input that is adapted to receive input voltages at TTL levels, for example, and has an output adapted to provide output voltages at CMOS levels, for example. The power saving switch includes a level shifter and a voltage control circuit both coupled to the bias node. The output voltage of the buffer is fed back to the power saving switch. When the output voltage is at a low CMOS level, the power saving switch uses the voltage control circuit to provide a first bias voltage to the bias node. When the output voltage is at a high CMOS level, the power saving switch uses the level shifter to provide a second bias voltage to the bias node. The second bias voltage is chosen such that it prevents current flow between the bias node and the buffer at a predetermined input cutoff voltage.