Patents Represented by Attorney Heller Ehrman White and McAuliffe LLP
  • Patent number: 6894539
    Abstract: A delay locked loop features a phase comparator. The phase comparator compares a phase of a reference clock signal obtained by dividing a buffered external clock signal with a phase of a feedback clock signal considering delay time of delay lines and inside circuits, and controls a shift register for controlling the delay lines in response not only a rising clock signal outputted from a clock buffer but also a falling clock signal depending on the comparison result, thereby rapidly locking an initial phase and tracking the phase in spite of fast delay variations by external noises.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 17, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Hoon Kim
  • Patent number: 6890738
    Abstract: Recombinant nucleotide sequences encoding mutated prolactin are described. Expression of the sequences result in mimics of a phosphorylated prolactin corresponding to a selected species. A particularly preferred mimic is mutated at serine 179 (corresponding to human PRL) where serine is substituted by an aspartate residue. This aspartate mutant is a very effective antagonist and shows no ability to stimulate Nb2 to cell proliferation.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: May 10, 2005
    Assignee: The Regents of the University of California
    Inventor: Ameae Walker
  • Patent number: 6887705
    Abstract: This invention concerns new PSTPIP polypeptides which are bound by and dephosphorylated by the PEST family of protein tyrosine phosphatases. The invention specifically concerns native murine PSTPIP polypeptides and their homologues in other mammals, and their functional derivatives. The invention further relates to nucleic acids encoding these proteins, vectors containing and capable of expressing such nucleic acid, and recombinant host cells transformed with such nucleic acid. Methods for inducing the plymerization of actin monomers in eukaryotic cells and assays for identifying antagonists and agonists of the PSTPIP polypeptides of the present invention are also provided.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: May 3, 2005
    Assignee: Genentech, Inc.
    Inventors: Laurence A. Lasky, Donald J. Dowbenko
  • Patent number: 6885578
    Abstract: The present invention generally relates to a NAND-type magnetoresistive RAM, and more specifically, to a NAND-type magnetoresistive RAM comprising a plurality of transistors connected in series as a NAND-type which can reduce the effective area per cell. Two or more NAND-type transistors sharing an adjacent source region and an adjacent drain region are connected in series, thereby reducing inactive regions. A read node connected to a bitline is shared by a plurality of transistors, thereby improving a read operation. As a result, the effective area per cell can be decreased, and the integration of a device can be improved.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: April 26, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seon Yong Cha
  • Patent number: 6884713
    Abstract: Methods for forming metal line of semiconductor device wherein via contact plug is formed without the deposition process of Ti/TiN liner layer and conductive layer filling a via contact hole so that the formation processes of a conductive layer for lower metal line and a conductive layer for via contact plug can be performed successively without interruption is disclosed.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: April 26, 2005
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Won Hwa Jin
  • Patent number: 6884678
    Abstract: A method for forming of a capacitor wherein an etching barrier layer comprising a stacked structure of a nitride film and a tantalum oxide film is disclosed. The method comprises the steps of: forming an etching barrier layer on an interlayer insulating film having a storage electrode contact plug therein, the etching barrier layer comprising a stacked structure of a nitride film and a tantalum oxide film; forming an oxide film on the etching barrier layer; selectively etching the oxide film and the etching barrier layer to form an opening exposing the storage electrode contact plug; depositing a storage electrode layer on the bottom and the inner walls of the opening; and removing the oxide film, whereby forming a storage electrode.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: April 26, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Su Park, Tae Hyeok Lee, Cheol Hwan Park
  • Patent number: 6882983
    Abstract: The present invention discloses a system and method for processing business transactions between trading partners using a central interactive platform. The processing may include comparing purchase order data and invoice data to identify matching information and non-matching information. If the information matches, the invoices are processed for payment. If the information does not match, the discrepancies are identified to the buying company or the selling company for resolution.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: April 19, 2005
    Assignee: Notiva Corporation
    Inventors: Thomas W. Furphy, David W. Bandych, John T. Marron, Jason A. Carreira
  • Patent number: 6878734
    Abstract: Ligands for the gastrin and cholecystokinin (CCK) receptors are provided, together with methods for preparing such ligands, and compounds which are useful intermediates in such methods. Pharmaceutical compositions comprising such ligands, methods for preparing such pharmaceutical compositions, and methods of treatment using these compositions also are provided.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: April 12, 2005
    Assignee: James Black Foundation Limited
    Inventors: Sarkis Barret Kalindjian, Ildiko Maria Buck, Katherine Isobel Mary Steel, Paul Trevor Wright, Matthew John Tozer, Michael John Pether, Caroline Minli Rachel Low
  • Patent number: 6875361
    Abstract: The present invention relates to a water purifying device including: a cell unit consisting of a high purity ceramic for obtaining far infrared ray, and having a shape according to a kind of water tank, a ring-shaped Volta cell consisting of a non-ferrous metal being provided in the cell unit; and a lump unit being connected to the cell unit through a metal coil, and consisting of ceramic, a conductive lump consisting of a non-ferrous metal being provided in the lump unit. Accordingly, the water purifying device is easily installed in the water tank, for disinfecting bacteria, restricting generation of bacteria, removing odor, and facilitating growth of aquatic plants and fishes. As a result, a number of changing water in the water tank can be considerably reduced, to improve efficiency.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: April 5, 2005
    Assignee: Redox Co., Ltd.
    Inventor: Gun Shik Park
  • Patent number: 6873465
    Abstract: An installation for increasing the daylight yield in a stadium provided with a playing surface, stands, and optionally a covering, includes an essentially vertical light-reflecting body to guide the light incident on the body towards the playing surface in the stadium. Preferably the reflecting body is arranged along the free peripheral edge of the covering of the stadium. In one embodiment the reflecting body includes a multi-layer construction of two corrugated sheets with a light-reflecting foil between them. The installation can increase the light yield in a covered stadium by between 30% and 50%.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: March 29, 2005
    Assignee: West 6 B.V.
    Inventor: Cornelis Groot
  • Patent number: 6873172
    Abstract: An automated laser diode testing and burn-in system is disclosed. Initial device data is obtained by applying current to the device at room temperature and measuring the device parameters. The device is then subjected to a burn-in process at higher temperatures. Device performance is monitored throughout the burn-in process. Upon termination of the burn-in process the devices are cooled to room temperature and the post burn-in device power is measured again under the same test conditions. If the device parameters have changed by more than a particular amount the device is rejected. Otherwise, the device is accepted and installed in the next level assembly.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: March 29, 2005
    Assignee: Bandwidth9, Inc.
    Inventors: Paul Cornelius, John Walsh, Yong Yim
  • Patent number: 6873192
    Abstract: A power-up detection apparatus comprises a voltage divider, a potential detector and a buffer. The voltage divider divides an inputted power voltage in a predetermined ratio. The potential detector compares a predetermined potential with a potential outputted from said voltage divider, and outputs the comparison result. The buffer changes the level of said comparison result when said comparison result outputted from said potential detector is maintained at a predetermined potential for a predetermined period. As a result, a semiconductor device can be stably initialized because a power-up signal is generated only when an externally inputted power voltage is maintained at a current state over a predetermined period although the state of the external power voltage is toggled by noise.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 29, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Seok Kang, Jae Jin Lee
  • Patent number: 6870785
    Abstract: A nonvolatile ferroelectric memory device having a multi-bit control function can store and sense multi-bit data in a ferroelectric memory cell. In the memory device, a plurality of cell array blocks generates a plurality of different sensing critical voltages in a reference timing strobe interval. As a result, in different time intervals, the plurality of sensing critical voltages are compared with a plurality of cell data sensing voltages applied from a main bitline. A data register array unit stores a plurality of cell data applied from the plurality of cell array blocks in response to a plurality of read lock signals activated at different timings in different time intervals, respectively. Therefore, the plurality of data bits can be stored in a cell.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: March 22, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 6869608
    Abstract: Immunologically active peptides which are derived from a novel immunodeficiency virus which has the designation MVP5180/91 are described. A diagnostic containing such a peptide and methods of detecting an antibody against a retrovirus that causes immune deficiency using such diagnostic composition are also described. A kit containing the immunologically active peptides is also described. An immunogen and method of immunizing a mammal against HIV infection using the immunologically active peptides is described. DNA encoding the peptides and methods of detecting nucleic acids encoding HIV viruses are also described.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: March 22, 2005
    Assignee: Dade Behring Marburg GmbH
    Inventors: Stefan Brust, Stefan Knapp, Manfred Gerken, Lutz G. Guertler
  • Patent number: 6870033
    Abstract: Humanized anti-IL-8 monoclonal antibodies and variants thereof are described for use in diagnostic applications and in the treatment of inflammatory disorders. Also described is a conjugate formed by an antibody fragment covalently attached to a non-proteinaceous polymer, wherein the apparent size of the conjugate is at least about 500 kD. The conjugate exhibits substantially improved half-life, mean residence time, and/or clearance rate in circulation as compared to the underivatized parental antibody fragment.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: March 22, 2005
    Assignee: Genentech, Inc.
    Inventors: Vanessa Hsei, Iphigenia Koumenis, Steven R. Leong, Leonard G. Presta, Zahra Shahrokh, Gerarado A. Zapata
  • Patent number: 6870779
    Abstract: A reset signal generating circuit and a nonvolatile ferroelectric memory device using the same are disclosed. The reset signal generating circuit generates a reset signal by using a self-bias circuit regardless of a slope time of a power voltage only when the power voltage rises beyond a predetermined voltage. As a result, the reset signal generating circuit may generate a stable reset signal having excellent operation characteristics at short intervals even when the supply of the power source is repeatedly intercepted. Additionally, the reset signal generation circuit may stabilize generation of control signals for controlling a nonvolatile FeRAM, thereby improving the operation characteristics of the memory device.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 22, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 6870034
    Abstract: A method for purifying proteins by Protein A chromatography is described which comprises removing contaminants by washing the solid phase with various intermediate wash buffers.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: March 22, 2005
    Assignee: Genentech, Inc.
    Inventors: Timothy N. Breece, Robert L. Fahrner, Jeffrey R. Gorrell, Kathlyn Pham Lazzareschi, Philip M. Lester, David Peng
  • Patent number: 6869539
    Abstract: Cost-effective processes and tools used therein are described that decontaminate sludge using remedial water in a closed and environmentally friendly system. Typical contaminants such as toxic metals, microorganisms, and toxic compounds are detoxified or destroyed by one or more remedial water treatments to sludge that is confined to the closed system. The closed system may comprise a covered rail road car, ISO container, or other large space into which the remedial water, and optionally, remedial gas, is applied by injection or other means. In a preferred embodiment, water is electrochemically activated at the site of use and injected through an array of pipes within the container. A large variety of other waters and combinations of water, and even air treatments are particularly useful in combination with the closed system for treating sludge.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: March 22, 2005
    Inventor: Richard G. Sheets
  • Patent number: 6867998
    Abstract: The present invention discloses a cell array block of a ferroelectric random access memory (FeRAM) and an FeRAM using the same. In the multi-bit line structure cell array block of the FeRAM having a sub bit line and a main bit line, and including a plurality of sub cell arrays for inducing a sensing voltage of the main bit line by converting a sensing voltage of the sub bit line into current, in order to overcome different data properties of the whole sub cell arrays due to delay time differences by positions of the sub cell arrays, a different size of sensing loads are selectively transmitted to the main bit line according to the positions of the operated sub cell arrays, or a different size of ferroelectric capacitors are used in a memory cell according to the positions of the sub cell arrays. As a result, the cell data properties of the whole cell array block are equalized for even distribution.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: March 15, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 6863782
    Abstract: Di(ketene acetals) are prepared by photoisomerizing the corresponding di(vinyl acetals).
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: March 8, 2005
    Assignee: A.P. Pharma, Inc.
    Inventors: Peter W. Newsome, A. Roger Frisbee, Zinovy Itov, April J. Morgan, Robert A. Noe