Patents Represented by Attorney, Agent or Law Firm Hickman Stephens & Coleman, LLP
  • Patent number: 5982833
    Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.
    Type: Grant
    Filed: August 6, 1996
    Date of Patent: November 9, 1999
    Assignee: VLSI Technology, Inc.
    Inventor: Michael R. Waters
  • Patent number: 5975308
    Abstract: A cuboid wafer container consists of a top bucket and a bottom bucket. The top bucket further consists of a square bucket and a cylindrical bucket, the same does the bottom bucket. The cylindrical bucket and the square bucket are connected through cushion to absorb vibration for protect the wafers from being damaged by the vibration. The wafer container according to the invention can be opened and sealed without screwing the buckets, so that damages occurred on the surfaces of wafers is reduced.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: November 2, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Jason Horng, Jason Hsia
  • Patent number: 5974245
    Abstract: The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveability, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: October 26, 1999
    Assignee: VSLI Technology, Inc.
    Inventors: Ying-Meng Li, Sunil V. Ashtaputre, Jacob Greidinger, Mark R. Hartoog, Moazzem M. Hossain, Siu-Tong Hui
  • Patent number: 5972183
    Abstract: A getter pump module includes a number of getter disks provided with axial holes, and a heating element which extends through the holes to support and heat the getter disks. The getter disks are preferably solid, porous, sintered getter disks that are provided with a titanium hub that engages the heating element. A thermally isolating shield is provided to shield the getter disks from heat sources and heat sinks within the chamber, and to aid in the rapid regeneration of the getter disks. In certain embodiments of the present invention the heat shields are fixed, and in other embodiments the heat shield is movable. In one embodiment, a focus shield is provided to reflect thermal energy to the getter material from an external heater element and provide high pumping speeds. An embodiment of the present invention also provides for a rotating getter element to enhance getter material utilization.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: October 26, 1999
    Assignee: SAES Getter S.p.A
    Inventors: Gordon P. Krueger, D'Arcy H. Lorimer, Sergio Carella, Andrea Conte
  • Patent number: 5967892
    Abstract: A video crane game including a display device, such as a video screen, for displaying images. A mechanical crane-like device provided over the display device includes an x-y assembly for allowing a player to control the movement of a selection head in an x-y plane. A z-movement device causes the selection head to move in a z-direction toward and away from the images of the display device. A sensor detects a location of the selection head with respect to the images displayed on the display device when the head is moved just above or contacts the display. A game controller controls the display of the images and determines a game outcome based on the location of the selection head with respect to the displayed images. The displayed images may include multiple selectable image targets, such as prize images associated with a prize, penalty areas, or images associated with a point score. A dispenser dispensing an award to a player of the game apparatus, such as tickets or prizes.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: October 19, 1999
    Inventor: Stephen P. Shoemaker, Jr.
  • Patent number: 5967514
    Abstract: An arcade game including a progressive bonus apparatus connected to a plurality of individual game units. The progressive bonus apparatus receives score contributions from each game unit to increase a progressive score. When players achieve a predetermined task on a game unit, they receive a non-monetary award based on the progressive score. Each game unit connected to the progressive bonus apparatus may take the form of an arcade-type game with a rotating wheel on which to base scoring. A playing piece is directed down a playing surface towards a target end, and the wheel is rotated according to the target that was hit by the playing piece. The position of the wheel when it stops rotating affects the score. A non-monetary award based on the score is dispensed to the player when the game is completed.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: October 19, 1999
    Assignee: RLT Acquisitions, Inc.
    Inventors: Bryan M. Kelly, Norman B. Petermeier, Matthew F. Kelly, J. Richard Oltmann
  • Patent number: 5961750
    Abstract: Nonevaporable getter alloys containing Zr, Co, and a third component A selected from the rare each metals and mixtures thereof, e.g., mischmetal. A most preferred alloy contains about 80.8 wt % Zr, about 14.2 wt % Co, and about 5 wt % A. These alloys are advantageous because they are suitable for general use, i.e., they have a relatively low activation temperature, are capable of sorbing a wide variety of gases, and minimize the environmental and safety risks associated with known nonevaporable getter alloys.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: October 5, 1999
    Assignee: SAES Getters, S.p.A.
    Inventors: Claudio Boffito, Alessio Corazza, Stefano Tominetti
  • Patent number: 5955872
    Abstract: A method for generating, in a switching power supply, an output voltage from an input voltage. The method includes the step of closing a switch in the switching power supply to permit current from the input source to flow through the inductor and the capacitor of the switching power supply, thereby building up an inductor current through the inductor and increasing the output voltage across the capacitor. If a combination of the output voltage and inductor current is satisfactory at the start of an off-time of the oscillator signal, the method opens the switch. If a combination of the output voltage and inductor current is unsatisfactory at the start of an off-time of the oscillator signal, the inventive method preferably keeps the switch closed past the off time of the oscillator signal to continue building up the inductor current through the inductor and increasing the output voltage across the capacitor.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: September 21, 1999
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Michael Arthur Grimm
  • Patent number: 5953236
    Abstract: A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (a) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (b) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (c) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (i) modifying the netlist pursuant to an engineering change order (ECO); and (ii) making an ECO placement of at least one cell into the layout area based upon the timing constraints while adjusting any affected nets as specified by the netlist. A layout tool implements the method on a computer system to form a portion of and integrated circuit fabrication system.
    Type: Grant
    Filed: October 31, 1995
    Date of Patent: September 14, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Moazzem Hossain, Bala Thumma, Sunil Ashtaputre
  • Patent number: 5942007
    Abstract: A dry cleaning system and method, in which specially designed or modified machinery is used in conjunction with a specific solvent which is derived from an organic/inorganic hybrid (organo silicone). In this class of organo silicones is a group known as cyclic siloxanes. The cyclic siloxanes present the basis for material composition of the solvent chemistry which allows this dry cleaning system to be highly effective. The cyclic-siloxane-based solvent allows the system to result in an environmentally friendly process which is, also, more effective in cleaning fabrics and the like than any known prior system. The siloxane composition is employed in a dry cleaning machine to carry out the method of the invention.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: August 24, 1999
    Assignee: GreenEarth Cleaning, LLP
    Inventors: Dieter R. Berndt, John McLeod Griffiss
  • Patent number: 5943591
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: August 24, 1999
    Assignee: VLSI Technology
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5917361
    Abstract: A low-noise output buffer in accordance with the present invention includes pre-driver circuitry coupled to core circuitry of an integrated circuit, output circuitry having a variable drive level that is responsive to the pre-driver output signal and powered by a first power supply, and noise reduction control circuitry coupled to the first power supply. The noise reduction control circuitry is powered by a second power supply which has less noise than the first power supply, and is arranged to develop a control signal that is coupled to the output circuitry to modify the drive level of the output circuitry to counteract noise detected on the first power supply. In some embodiments, the noise reduction control circuitry includes a first transistor and the output circuitry includes a second transistor which are arranged to form a stacked transistor pair.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: June 29, 1999
    Assignee: VLSI, Technology
    Inventors: Jeffrey F. Wong, Wassem Ahmad
  • Patent number: 5917191
    Abstract: A method for measuring surface topography characterized by making multiple scans of the surface with a laser scanning unit and utilizing the multiple scans to create representations of the surface's topography. The surface topography data can also be used to calculate the compressive or tensile stress caused by a thin film applied to the surface of a semiconductor wafer. The apparatus of the present invention scans a laser beam across a surface in an x direction, and detects displacements of a reflected portion of the laser beam in a z direction. A pair of photodetectors are used to translate z direction displacements of the reflected beam into analog signals which are digitized and input into a microcomputer for analysis. The multiple scans of the surface are preferably accomplished by placing the workpiece on a pedestal which can be rotated to various angular positions.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: June 29, 1999
    Assignee: Ann F. Koo
    Inventor: David Cheng
  • Patent number: 5908579
    Abstract: A process is disclosed for producing non-evaporable getter materials having high porosity and improved gas sorption rates. The process includes mixing together a metallic getter element, a getter alloy and a solid organic compound, all three components being in the form of powders having specific particle sizes. The mixture is subjected to a compression of less than about 1000 kg/cm.sup.2 and is sintered at a temperature between about C. and about C. for a period between about 5 minutes and about 60 minutes. The getter material thus obtained is used to produce getter bodies shaped as pellets, sheets or discs having better mechanical strength than similar bodies of other getter material having comparable porosity.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: June 1, 1999
    Assignee: SAES Getters, S.p.A.
    Inventors: Andrea Conte, Sergio Carella
  • Patent number: 5907262
    Abstract: An amplifier circuit that offers high bandwidth operation and a high slew rate is disclosed. The amplifier circuit may also have an input voltage swing down to the negative rail which is particularly suitable for low voltage applications having a single power source. In one embodiment, the amplifier circuit amplifies a difference voltage between first and second input voltages to produce an output voltage, and includes: an analog voltage-to-current converter for receiving the first and second input voltages and producing complementary current signals; and a complementary mirror output stage coupled to receive the complementary current signals at respective mirror circuits.
    Type: Grant
    Filed: November 18, 1996
    Date of Patent: May 25, 1999
    Assignees: Maxim Integrated Products, Inc., Gain Technology Corporation
    Inventors: Jerald G. Graeme, Madhav V. Kolluri