Abstract: An interleaver generates a valid interleaved data address for each iteration i of the mapping by the interleaver without employing a multiplication operation. The interleaver includes an address generator comprises two counters, bit-reverse and index tables, and an accumulation register array. The interleaver further comprises two adders, two registers storing tentative address values addressi and addressi+1, and select logic including a comparator, two buffers, and a multiplexer (mux). Two counters are employed to allow the interleaver to generate at least one valid address for each iteration, and a tentative address is generated from each output value of the two counters. Each iteration generates an output interleaved address. A tentative address is generated by using a portion of the counter value as an address to select a corresponding entry from each of the bit-reverse and index tables and the accumulation register array.

Abstract: A circuit and method for equalization of a communication signal received over a communication system transmission line using switched filter characteristics. Equalization for frequency-independent and frequency-dependent attenuation of the communication signal is accomplished with a linear equalization channel which includes an input biasing circuit which provides a common input signal to two parallel amplifier paths. One path includes a wideband, fixed-gain, frequency-independent amplifier stage. The other path is a wideband multiplier amplifier stage in series with a wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic. The outputs of the fixed-gain wideband frequency-independent amplifier stage and wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic are both tied in common to the input of a wideband gain buffer amplifier stage, which has a switchable high-frequency boost frequency response characteristic.

Abstract: A system is disclosed that services a plurality of queues associated with respective data connections in a packet communication network such that the system guarantees data transfer delays between the data source and the destination of each data connection. This is achieved in two stages. The first stage shapes the traffic of each connection such that it conforms to a specified envelope. The second stage associates timestamps with the packets released by the first stage and chooses for transmission from among them the one with the smallest timestamp. Both stages are associated with a discrete set of delay classes. The first stage employs one shaping structure per delay class. Each shaping structure in turn supports a discrete set of rates and employs a FIFO of connections per supported rate. A connection may move between FIFOs corresponding to different rates as its rate requirement changes.

Abstract: A phase-locked loop (PLL) employs a ring oscillator for the voltage-controlled oscillator (VCO), and the ring oscillator comprises an odd number of inverting stages operating at a given frequency. The frequency of the ring oscillator is determined by the delay through each stage and the number of stages. The output signal of each stage has a phase determined by the number of stages, and each stage provides its output signal with a different phase. The VCO of the PLL selects phases of the ring oscillator to clock the counter of the feedback divider of the PLL. Each phase is selected by a multiplexer (mux) under the control of a finite state machine that monitors the output of the counter. When the counter completes a full count cycle on one phase of the ring oscillator, the finite state machine selects a different phase of the ring oscillator to clock the counter for the next count cycle.

Abstract: An iterative decoder decodes a frame of encoded data that includes error detection information, and terminates the iterative decoding based on a comparison of the decoded frame with the error detection information. The iterative decoder may have a maximum number of specified iterations, but may terminate the number of iterations early under specified conditions. The encoded data includes error detection information for parity check calculation. Error detection information may be in accordance with an error detection code, such as a cyclic redundancy check (CRC) code. After each iteration of decoding, a parity check is calculated for the decoded frame. Early termination of decoding may occur prior to an intermediate iteration threshold M of iterations when the parity check value of the decoded frame is equivalent to the parity check value calculated from the error detection information.

Abstract: A data recording system employs parallel iterative decoding of soft output samples representing encoded data read from a storage medium. The iterative decoder reads packets of data from a sector of the medium, each packet containing soft output samples representing data encoded with a concatenated code formed from N component codes, N a positive integer. The iterative decoder employs I decoding iterations, I a positive integer. Each packet has a length substantially equal to the sector length divided by N. For an exemplary magnetic recording system, encoded data read from a sector of a magnetic medium is partitioned into N packets of length 4096/N. The first packet is passed to the first component code decoder of a parallel iterative decoder. When the second packet is ready to be passed to the first component code decoder, the decoded output values of the first packet in the first decoder are passed to the second component code decoder. The second packet is then applied to the first component code decoder.

Abstract: A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than l and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits.

Abstract: A shared correlator system and method for a code division, multiple access (CDMA) receiver employs pipeline processing and information tags for sharing vector generation and correlation operations between processing units. A signal input to the CDMA receiver is provided as, for example, In-phase channel (I) and quadrature-phase channel (Q) sample vectors IREC and QREC. Sample vectors IREC and QREC are applied to the shared correlator of the CDMA receiver. Processing units request correlation operations by the shared correlator in which matched filter pseudo-noise (PN) vectors are correlated with the I and Q sample vectors IREC and QREC. The shared correlator schedules correlation operations requested by processing units, generates matched-filter, PN vectors with associated identification tags for the correlation operations, and provides correlation results for the correlation operations.

Abstract: A differential voltage-controlled oscillator (VCO) employs a pair of accumulation-mode varactors driven with a differential control voltage to generate a differential oscillating waveform. The differential control voltage is formed from a pair of level-shifted input differential control voltage components. Level shifting of the input control voltages and driving the varactors with a differential control voltage allows for biasing of the varactors over a substantial range of capacitance variation. Such differential VCO may be employed within a phase-locked loop (PLL) circuit, with the pair of input control voltages being provided by the loop filter of the PLL circuit. The differential VCO comprises a differential control voltage to voltage converter (CV2VC) coupled to an LC-tank VCO. To improve common-mode noise rejection of the LC-VCO, the inductors of the LC-tank may be AC-coupled to the supply voltage, and the output differential oscillating waveform may be AC-coupled to the LC-tank through capacitors.

Abstract: A phase tracker receives a signal component xn and forms a phase- and gain-corrected signal zn. In particular, the phase tracker performs a Hilbert transform of xn to produce a quadrature phase component yn to form the constellation defined by (xn, yn). Consequently, phase rotation and gain adjustment are combined into a linear transform of the constellation defined by (xn, yn). The linear transform zn=&agr;xn+&bgr;yn employs two coefficients &agr; and &bgr;. The coefficients &agr; and &bgr; of the linear transform are derived so as to provide an optimal solution according to minimum mean square error. Approximations to the coefficients &agr; and &bgr; of the linear transform may be iteratively determined with a stochastic gradient method. Advantages of employing the phase- and gain-corrected signal zn as an I-phase detection result of a demodulator include 1) the phase rotation and gain adjustment are combined into one operation, and 2) the a sine/cosine lookup table is not employed.

Abstract: An iterative decoder arranges calculation of updated reliability values for a current iteration of an iterative decoder so as to reduce the number of comparison operations. The variables for the magnitude and sign of the updated reliability value are initialized. A search of the previous reliability values generates first and second minimum magnitude values for each row (if the iterative decoder is decoding in the horizontal direction) or column (if the iterative decoder is decoding in the vertical direction). A test determines whether the magnitude of the previous reliability value is greater than the first minimum magnitude value m1. If so, the magnitude of the updated reliability value is set as the value m1. Otherwise, the magnitude of the updated reliability value is set as the second minimum magnitude value m2. The sign of the updated reliability value is tracked and assigned once the updated reliability value is set.

Abstract: Rate detection of a data rate within a sequence of transmitted symbols employs correlation to calculate estimates of the auto-correlation values, or estimated coefficients, of the sequence. When the sequence of transmitted symbols includes repeated symbol values, the auto-correlation values indicate a degree of self-similarity within the sequence. A decision statistic may be formed from the auto-correlation values. The self-similarity of the auto-correlation values may be employed as a decision statistic with associated hypothesis test pair values. Various decision methods may be implemented to compare auto-correlation values to thresholds based on the hypothesis test pair values. Based on the comparison, the data rate of the sequence may be determined. Once the information is determined related to the data rate, the information may be employed by a Viterbi detector to adjust the decoding rate for decoding the symbols.

Abstract: A packet network employing a reservation-based protocol system includes routers having processing sections that schedule message processing of the protocol's control messages adaptively based on link utilization. A scheduler of the processing section employs a round-robin scheduling with adaptive weight assignment to allocate processing capacity for control messages. For the RSVP protocol, for example, messages are grouped in classes, and link utilization of the packet flows for each message class is monitored. Weights corresponding to a portion of the processing section's processing capacity are allocated to each message class. The weights are defined based on link utilization for the message class and average message queue length. For processing sections monitoring multiple links, weights are further defined for super-classes based on overall link utilization. Weights may change as link utilization and average message size changes.

Abstract: A packet filter for a router performs generalized packet filtering allowing range matches in two dimensions, where ranges in one dimension at least one dimension is defined as a power of two. To associate a filter rule with a received packet EP, the packet filter employs a 2-dimensional interval search and memory look-up with the filter-rule table. Values of sm of filter-rule rm=(sm,dm) in one dimension are desirably ranges that are a power of two, such as prefix ranges, which are represented by a binary value having a “length” defined as the number of bits to of the prefix. The dm may be single points, ranges defined as prefix ranges, and/or ranges defined as continuous ranges. The packet filter employs preprocessing of the filter-rules based on prefix length as a power of 2 in one dimension and decomposition of overlapping segments into non-overlapping intervals in the other dimension to form the filter-rule table.

Abstract: A semiconductor device includes a semiconductor layer, prelayer, refractory layer, and conductive layer. The conductive layer includes an ohmic contact layer, and may also include a barrier layer, of a highly stable, low-resistance element or compound, such as Au or Ti, which is formed on the refractory layer. The refractory layer is a material that does not react with, or dissociate from, either the prelayer or the conductive layer when the semiconductor device is exposed to relatively high temperatures. The refractory layer material may be metal suicides, phosphides, or nitrides. The material of the prelayer is selected to minimize strain between the prelayer, the refractory layer and the semiconductor layer to provide a relatively strong bond between the refractory layer and semiconductor. The prelayer may be selected to provide relatively high current injection to the semiconductor, and may further form a low Schottky barrier height with the semiconductor.

Abstract: A packet filter method and apparatus for a router employs an algorithm that decomposes a set of n filter rules of a k-dimensional space into sets of rule segments associated with non-overlapping intervals in each dimension. Such packet filter may be employed for layer four switching applications. Bit-parallel processing may be employed to compare each interval with corresponding fields of a packet received by the router. Bitmaps defined by the sets of rule segments, and so related to the corresponding filter rules are associated with the intervals. The interval bitmaps are combined to form a filter rule bitmap that identifies and associates one or more filter rules with the packet.

Abstract: An error-correction process enables or disables error-correction in a cellular or wireless unit so as to conserve power of a battery or other power storage unit of the cellular or wireless unit. The error-correction process includes receiving a datablock having a checksum value and an encoded payload, the encoded payload includes one or more parity bits for error-correction of bit values within the encoded payload. If the checksum value is equivalent to a checksum value calculated for the encoded payload, then the error-correction process removes the parity bits from the encoded payload and provides the remaining encoded payload bits as the error-corrected data. Otherwise, if the checksum and calculated checksum are not equivalent, error-correction of the encoded payload is enabled.

Abstract: A general rate N/(N+1) (0, G), code construction, e.g., for a magnetic recording system, allows for encoding or decoding of a dataword having N elements, N preferably being an integer multiple of eight. The dataword is divided into N/8 bytes of binary data that are encoded as a run-length limited (RLL) codeword in accordance with the general rate N/(N+1) (0, G) code construction. The general rate N/(N+1) (0, G) code construction is characterized by the constraints (d=0, G=(N/4)+1, l=N/8, r=N/8). the N/(N+1) (0 (N/4)+1, N/8, N/8) RLL codeword is constructed from the dataword in accordance with 1) pivot bits identifying code violations related to the constraints, 2) correction bits set to correct code violations, and 3) preserved elements having values not included in the code violations.

Abstract: A system detects the presence of NTSC co-channel interference and enables NTSC comb-filtering when the NTSC signal is detected. The system comb-filters the baseband signal to generate a filtered baseband signal, and accumulates the noise power of the baseband and filtered baseband signals. The noise power of the baseband and filtered baseband signals is compared by forming a difference between the two noise powers, and the system detects the NTSC signal when the difference exceeds a threshold T. The threshold T is related to a product of a signal power of the baseband signal and a minimum carrier to noise ratio for the ATSC system.

Abstract: A digital filter receives signals from each stage of a MASH delta-sigma modulator and filters noise components from the signals prior to combination as a single sequence of values decimation. Each stage of the MASH delta-sigma modulator provides an output sequence of one-bit, binary values, which are then filtered to remove high-order, out of band quantization noise. After filtering, the output sequences are then combined through a cascade-combiner, which may be similar to the pre-processing stage of a MASH delta-sigma modulator architecture. The digital filter processes signals of each stage separately. Consequently, the digital filter does not perform multiplication of two, multi-bit values. Multiplication of two values, the first of which is a one-bit, binary value, may be implemented with a multiplexer selecting either the second value or a zero value based on the first one-bit, binary value (i.e., logic 1 or 0, respectively).