Patents Represented by Attorney IP & T Group LLP
  • Patent number: 8344800
    Abstract: There is provided a repeating system for cancellation of a feedback interference signal, including: a PA (Power Amplifier) for power-amplifying an output signal; a feedback ICS (Interference Cancellation System) for canceling a feedback interference signal and detecting a residual error; a pre-distorter for compensating for an error of the PA by applying pre-distortion and compensating for the residual error by using information on the residual error detected by the feedback ICS to linearize the characteristic of the PA; and a control unit for controlling the feedback ICS and the pre-distorter.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 1, 2013
    Assignee: Airpoint
    Inventors: Sung-Jun Baik, Joong-Han Choi
  • Patent number: 8344346
    Abstract: A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Beom Baek, Ja Chun Ku, Young Ho Lee, Jin Hyock Kim
  • Patent number: 8344771
    Abstract: A delay locked loop (DLL) of a semiconductor integrated circuit includes a first delay line configured to variably delay a source clock signal and output a locked clock signal, a phase comparator configured to compare the phase of the source clock signal with the phase of a feedback clock signal, a second delay line configured to variably delay the locked clock signal, a first delay controller configured to control the first delay time of the first delay line, a second delay controller configured to control the minimum delay time of the second delay line, and an operation mode controller configured to control the first and second delay controllers in response to an output signal of the phase comparator, and switch operation modes of the first and second delay controllers depending on locking state of the delay lines.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong-Suk Shin
  • Patent number: 8345471
    Abstract: A magneto-resistance element is provided. The magneto-resistance element includes an underlying layer including a main metal selected from electrically conductive metals and an auxiliary metal selected from transition metals, a first magnetic layer stacked on the underlying layer, an insulation layer stacked on the first magnetic layer, and a second magnetic layer stacked on the insulation layer.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ha Chang Jung
  • Patent number: 8344751
    Abstract: An impedance code generation circuit includes a first code generation unit configured to compare a voltage of a calibration node with a reference voltage and generate a first impedance code, a code modification unit configured to generate a modified impedance code by performing an operation on the first impedance code according to a setting value, and a second code generation unit configured to generate a second impedance code based on the modified impedance code.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Hee Cho
  • Patent number: 8343820
    Abstract: A method for fabricating a vertical channel type non-volatile memory device including a plurality of memory cells stacked along channels protruding from a substrate includes: alternately forming a plurality of first material layers and a plurality of second material layers over the substrate; forming a buffer layer over the substrate with the plurality of the first material layers and the plurality of the second material layers formed thereon; forming trenches by etching the buffer layer, the plurality of the second material layers, and the plurality of the first material layers; forming a material layer for channels over the substrate to fill the trenches; and forming the channels by performing a planarization process until a surface of the buffer layer is exposed.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Kyun Jung
  • Patent number: 8339191
    Abstract: A reference voltage generation circuit includes a driving control unit configured to output an enable signal during a first time period in response to a power-on reset (POR) signal, a reference voltage generation unit configured to have an initial operation determined in response to the enable signal and to output a reference voltage maintained at a constant voltage level after the first time period, and a reference voltage control unit configured to fix the voltage level of the reference voltage to a first voltage upon a voltage level of the reference voltage being increased to at least a set voltage level.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: December 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Beom Choi
  • Patent number: 8339871
    Abstract: Herein, a voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: December 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Woo-Seung Han, Khil-Ohk Kang
  • Patent number: 8339150
    Abstract: A semiconductor integrated circuit includes a bump pad through which data is outputted, a probe test pad having a larger size than the bump pad, a first output drive unit configured to drive the bump pad at a first drivability in response to output data, a second output drive unit configured to drive the probe test pad at a second drivability higher than the first drivability in response to the output data, and a multiplexing unit configured to transfer the output data to the first output drive unit or the second output drive unit in response to a test mode signal.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 25, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Byung-Deuk Jeon, Dong-Geum Kang, Young-Jun Yoon
  • Patent number: 8334207
    Abstract: A method for fabricating a semiconductor device includes providing a substrate including cell regions and peripheral regions; selectively forming a gate conductive layer over the substrate in the peripheral regions, forming a sealing layer over the substrate with the gate conductive layer formed thereon, forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate, planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer, and forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: December 18, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Ji-Min Lim, Kyung-ho Hwang
  • Patent number: 8334706
    Abstract: An impedance calibration mode control circuit includes: a first signal generating unit configured to generate a first calibration control signal in response to a ZQ calibration command received after a power-up operation; and a second signal generating unit configured to generate a second calibration control signal during a refresh operation of a semiconductor device.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: December 18, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: In-Jun Moon
  • Patent number: 8335107
    Abstract: A semiconductor memory device comprises memory blocks having a plurality of memory cells coupled to a plurality of bit lines, a first latch group coupled to a sense node and configured to store data to be programmed into memory cells, where the memory cells are coupled to the bit lines and the sense node is coupled to at least one of the bit lines, a second latch group coupled to the sense node and configured to receive data of the first latch group, and a sense node voltage control circuit configured to control a voltage of the sense node according to data stored in the first latch group.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: December 18, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Haeng Lee
  • Patent number: 8329522
    Abstract: A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung-Hee Park
  • Patent number: 8330531
    Abstract: An internal negative voltage generation device includes a first internal negative voltage generation block configured to generate a first internal negative voltage which is lower than a ground voltage; a second internal negative voltage generation block configured to generate a second internal negative voltage according to the first internal negative voltage, the second internal negative voltage being higher than the first internal negative voltage and lower than the ground voltage; and an initial driving block configured to additionally drive a second internal negative voltage terminal to the first internal negative voltage during an initial set time interval of an active operation time interval.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Patent number: 8331174
    Abstract: A semiconductor memory device includes: a repair address generation unit configured to generate a repair address signal in response to a first address signal; a line choice address generation unit configured to generate a line choice address signal by combining the first address signal and the repair address signal according to a determination as to whether the repair address signal is to be used; and a cell line decoding unit configured to select one of a normal cell region and a redundancy cell region according to the determination, and select one of a plurality of local cell lines provided in the selected cell region in response to the line choice address signal.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seong Nyuh Yoo, Duck Hwa Hong, Saeng Hwan Kim
  • Patent number: 8330533
    Abstract: A semiconductor device includes a first internal voltage driving unit configured to drive an internal voltage, a second internal voltage driving unit configured to drive the internal voltage in an operation period corresponding to an enable signal, a current amount detection unit configured to detect amount of current supplied by the first internal voltage driving unit, and a current amount comparison unit configured to compare the amount of detected current by the current amount detection unit with amount of a reference current, and determine whether or not to activate the enable signal in response to a comparison result.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chul Kim
  • Patent number: 8330215
    Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
  • Patent number: 8331190
    Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sun-Hyuck Yon, Kee-Teok Park
  • Patent number: 8329550
    Abstract: A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, and growing an epitaxial layer within the second trench.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min-Jung Shin
  • Patent number: 8331170
    Abstract: A data transfer circuit includes a first driver configured to drive a first line with data, a pattern alteration unit configured to change a pattern of the data transferred through the first line and produce a pattern-changed data, a second driver configured to drive a second line with the pattern-changed data; and a pattern restoration unit configured to receive the pattern-changed data transferred through the second line and restore the pattern of the data before the pattern change.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Shin-Ho Chu