Patents Represented by Attorney J. Dennis Moore
  • Patent number: 7177611
    Abstract: A hybrid digital and analog phase locked loop. A voltage controlled oscillator is provided, having a fine tune input, a coarse tune input and an output. A frequency divider has an input connected to receive a signal provided by the output of the voltage controlled oscillator, and has an output for providing a signal having a frequency that is divided with respect to a signal provided to its input. A phase detector is connected to receive a reference input signal having a reference frequency at a first input thereof and is connected to receive the signal provided by the output of the frequency divider. The phase detector has an output for providing a phase error signal. An analog is circuit configured as a proportional filter and is connected to receive the phase error signal and to provide a fine tune signal at the fine tune input of the voltage controlled oscillator.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: February 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Stanley Jay Goldman
  • Patent number: 7162684
    Abstract: Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which a left-hand portion of the parity check matrix is arranged as an identity macro matrix, each entry of the macro matrix corresponding to a permutation matrix having zero or more circularly shifted diagonals. The encoder circuitry includes a cyclic multiply unit, which includes a circular shift unit for shifting a portion of the information word according to shift values stored in a shift value memory for the matrix entry, and a bitwise exclusive-OR function for combining the shifted entry with accumulated previous values for that matrix entry. Circuitry for solving parity bits for row rank deficient portions of the parity check matrix is also included in the encoder circuitry.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Dale E. Hocevar
  • Patent number: 7138830
    Abstract: An output buffer having a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level and controls the voltage at the gates of the first pull-up transistor and the first pull-down transistor to provide the logic level at the output node. A second pull-up transistor and a second pull-down transistor are connected in series between the two nodes of the power supply, their common connection node being connected to the output node. A control circuit provides an output indicating when the supply voltage is below a predetermined level.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: November 21, 2006
    Assignee: Texas Instrument Incorporated
    Inventor: Christopher T. Maxwell
  • Patent number: 7135843
    Abstract: The circuit provides a type of switching power supply device that can reduce the ripple voltage generated in the output when switching is performed in the step-down/step-up control mode. Control part (CTRL) operates as follows: corresponding to the detection value of input potential detecting part 20, the step-down control mode/step-up control mode is switched; in each control mode, the clock signal generated by comparator 50 corresponding to output potential Vout is fed back to primary circuit (PRI)/secondary circuit (SEC); in this case, corresponding to the control mode, multiplexer 60 switches the input sign of transconductance amplifier 40 corresponding to the control mode.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: November 14, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Katsuya Ikezawa
  • Patent number: 7134061
    Abstract: A scan test circuitry design imbedded on an SoC having the scan architecture of a VLCT platform is disclosed herein. This BIST circuitry design that is not limited in the number of scan test ports supported includes at least one scan chain group having a corresponding clock domain that couples to receive test stimulus data. Each scan chain group has a corresponding test mode signal to shift the test stimulus data at a shift clock rate derived from its corresponding clock domain. A controlling demultiplexer connects to each multiplexer unit within each scan chain group to provide control signals for shifting in the test stimulus. A clock control mechanism provides a control signal for each scan chain to shift test stimulus and capture resultant data. Furthermore, when a simultaneous test mode signal is enabled, the clock control mechanism couples to each scan chain to enable simultaneous capture of each scan chain group.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: November 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Anupama Aniruddha Agashe, Nikila Krishnamoorthy, Anindya Saha, Rubin A. Parekhji
  • Patent number: 7116158
    Abstract: A bandgap reference circuit as may be used in ultra-low current applications is provided. An exemplary bandgap circuit can be configured to generate a positive temperature coefficient without the need for a resistor to offset a negative temperature coefficient. In accordance with an exemplary embodiment of the present invention, a bandgap circuit comprises a negative temperature coefficient generated from a junction device and a positive temperature coefficient generated from an FET-based device. An exemplary junction device can comprise a bipolar, junction diode or any other device for generating a negative temperature coefficient, while an exemplary FET-based device comprises a gate-drain connected device configured to provide a gate-source voltage having a positive temperature coefficient coupled in series with the bipolar device.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: October 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: John C. Teel, Tony R. Larson
  • Patent number: 7116172
    Abstract: A circuit topology for gain boosted high-swing folded cascode has been improved to maximize the available dynamic range in applications having low supply voltage requirements. The circuit includes an improved gain boost amplifier that maximizes the available dynamic range for applications having low supply voltage requirements. The improved gain boosting amplifier includes a differential pair of input transistors connected to a current mirror, wherein a pair of current sources supply current to each lead of the current mirror. One lead of the current mirror is level-shifted by a transistor coupled to another current source, wherein the coupling of the transistor and the current source form the output of the amplifier. Effectively, the amplifier consists of a level shifter and a series common-drain, common-gate amplifier. A reduction in transconductance gm from the series combination is compensated by a current mirror ratio (K:1) between the level shift and the common-drain, common-gate amplifier.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: October 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick P. Siniscalchi
  • Patent number: 7116169
    Abstract: A driver apparatus comprising a signal switching circuit coupled for receiving an actuation signal and generating a first and a second control signal in response to the actuation signal; a first control circuit and a second control circuit coupled with the signal switching circuit; the first and second control circuits generating first and second drive control signals in response to the first and second control signals; first and second current generating circuits coupled with the first and second control circuits and coupled with a lower voltage rail; the first and second current generating circuits presenting first and second drive signals at first and second output loci in response to the first and second drive control signals.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: October 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: John W. Fattaruso
  • Patent number: 7109802
    Abstract: A differential to single-ended signal transfer circuit that allows increased gain and improved AC performance while reducing power supply voltage requirements. The transfer circuit includes a first operational transconductance amplifier (OTA), a second operational amplifier (OPA), first and second controlled current sources, a third current source, and first and second bipolar junction transistors. The inverting and non-inverting inputs of the transfer circuit are provided at the inverting input and the non-inverting input, respectively, of the OTA, which is coupled to the first and second controlled current sources to form a current mirror with tracking feedback. The output voltage of the transfer circuit is provided at the emitter of the first transistor, the base of which is connected to the non-inverting input INp. The first transistor is coupled to the third current source in an emitter follower configuration to provide both current gain and impedance matching.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: September 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Sergey Alenin
  • Patent number: 7110204
    Abstract: The present invention achieves technical advantages as an improved Parallel Damping scheme suitable for very-low-supply preamp operation. The improved Parallel Damping Scheme accurately generates a programmable Iw flowing through the write head while compensating for a leakage current path through a Parallel Damping resistor.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: September 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Davy H. Choi
  • Patent number: 7109697
    Abstract: An operational amplifier having temperature-compensated offset correction. The amplifier includes an operational amplifier circuit, that has a first input field effect transistor (FET) having a gate connected to receive a first input signal, and a second input FET having a gate connected to receive a second input signal, the first and the second input FETs being connected together to receive a first bias current, and also being connected to respective sides of a first current mirror. A correction amplifier circuit is also provided, that has a first correction FET having a gate, and a second correction FET having a gate, the first and the second correction FETs being connected together to receive a second bias current, and also being connected to respective sides of a second current mirror.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Amer Hani Atrash, Shanmuganand Chellamuthu
  • Patent number: 7064593
    Abstract: A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current ‘Ioff’ specification without incorporating a diode in pull-up path of a bus-hold circuit is disclosed herein. Specifically, the bus-hold circuit includes a first subcircuit portion operable to provide the bus-hold feature of the circuit connected to a second subcircuit portion. The second sub-circuit portion provides the over-voltage tolerance feature and minimizes the leakage current in the bus-hold circuit. The bus-hold circuit in accordance with the present invention is enhances the performance of the bus-hold current by eliminating the voltage drop across the diodes customarily included within known bus-hold circuit designs. Thereby, this implementation eliminates the negative diode effect on the minimum high sustaining bus-hold current (IBHH) at low supply voltages due to the voltage drop across the diode.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Gene B. Hinterscher, Susan A. Curtis
  • Patent number: 7061214
    Abstract: A single-inductor dual-output buck converter and control method that facilitates power conversion by converting a single DC power source/supply into two separate DC outputs, each of which can be configured to provide a selected/desired voltage by selection of respective duty cycles. The topology of the inverter includes a pair of diodes or switches that can selectively re-circulate inductor current. The converter is generally operated at a fixed frequency with four stages of operation. A first and third stage of operation provide power to a first and second output, respectively. A second and fourth stage of operation re-circulate inductor current and can partially recharge a battery type power source. The power output for each stage (voltage and current) can be selectively obtained by computing and employing appropriate time periods for the stages of operation that correspond to appropriate duty cycles.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: June 13, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Valerian Mayega, Jun Chen, James L. Krug, David W. Evans
  • Patent number: 7061325
    Abstract: A system and method for providing digital compensation and correction for an amplifier. The system is configured to provide a digitally compensated representation of a first amplified analog signal indicative of a first parameter based on a digital representation of the first amplified analog signal and a digital representation of a second analog signal indicative of a second parameter. The digitally compensated representation of the first amplified analog signal is determined by applying a pre-stored compensation factor to an offset adjustment calculation for the second parameter to provide a compensated offset adjustment. The compensated offset adjustment is combined with an adjusted gain to provide an offset and gain correction for weighting the first parameter to provide the digitally compensated representation of the first parameter. The adjusted gain can be determined by applying a pre-stored gain factor data to the second parameter.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: June 13, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Jeanne Krayer Pitz
  • Patent number: 7061217
    Abstract: A power switching circuit includes a power MOS transistor that has a maximum source-drain voltage substantially higher than a permissible gate-source voltage, and that has a current path connected in series with a load between first and second supply terminals, and comprising a gate driver circuit that drives the gate of the power MOS transistor directly from the supply voltage. A gate driver circuit has a pair of series-connected switching transistors connected between the first and second supply terminals. An interconnection node between the switching transistors is connected to the gate of the power MOS transistor. The gate driver circuit further includes a reference voltage source and a voltage comparator comparing the gate voltage of the power MOS transistor with the reference voltage to provide a disabling output that disables one of the switching transistors when the gate voltage of the power MOS transistor reaches the reference voltage.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: June 13, 2006
    Assignee: Texas Instruments Deutschland, GmbH
    Inventors: Erich Bayer, Hans Schmeller
  • Patent number: 7056767
    Abstract: A flip chip semiconductor device having non-solder contact terminals is assembled by securing the chip and substrate with a rapidly thermosetting adhesive. The process is amenable to various bump and substrate materials, and has the advantage of simultaneously adhering the components and of providing a void free underfill. The process makes use of absorption of infrared energy by the chip to heat the adhesive and cause it to flow prior to rapidly solidifying from the center outwardly. The rapid assembly, using a simple infrared exposure apparatus is compatible with reel to reel, or other highly automated in-line processes.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: June 6, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Jimmy Liang, Kevin Jin, T. T. Chiu
  • Patent number: 7050323
    Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: May 23, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroshi Takahashi, Osamu Handa, Rimon Ikeno
  • Patent number: 7050463
    Abstract: An automatic bit-rate detection scheme (30) for use in SONET/SDH transceivers (12, 14) that uses only one clocking frequency (clk), is all digital, and requires less than 250 microseconds to detect a new data bit-rate. The present invention analyzes events that are guaranteed to be present in all SONET data streams. A1 and A2 framing bytes (22,24) occur at 125 microseconds intervals in all SONET signals. The bit transitions in the framing bytes represent the minimum transition intervals of the received data. The present invention examines this bit interval to determine the operating frequency of the received data. A set of combinational logic circuits (70, 80, 90) are used to detect specific data bit patterns which appear in the A1 and A2 SONET framing bytes, such as “010” and “101”. The combinational circuit looks for specific patterns of data bits occurring at a specific communication rate.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: May 23, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: James B. Cho, Harry W. Hartjes
  • Patent number: 7046306
    Abstract: In one embodiment, a method for processing a video signal includes: (1) receiving and storing luminance and chrominance information for each pixel in a first portion of the signal; (2) receiving luminance and chrominance information for each pixel in a second portion of the signal; (3) determining an estimated motion vector for each particular pixel of the second portion by comparing the luminance and chrominance information of the particular pixel to the stored luminance and chrominance information for one or more pixels in a search area of the first portion to determine a pixel in the search area that most closely matches the particular pixel and determining the estimated motion vector according to the particular pixel and the most closely matching pixel; (4) using the estimated motion vector to access the chrominance information for the most closely matching pixel; (5) using a three-dimensional comb filter to filter the chrominance information for the particular pixel and for the most closely matching pixe
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Fan Zhai, Karl H. Renner
  • Patent number: 7042713
    Abstract: A handheld computing device includes a display screen, a main housing portion, a removable case, and a stand member. The main housing retains the display screen. The removable case is adapted to slidably fit over at least part of the main housing. The stand member is pivotably coupled to the case. The stand member, the case, and the main housing are configured so that the main housing may be retained at a tilt angle relative to a surface by the stand member and the case when the case is laying on the surface and when the stand member is pivoted relative to the case to form a stand angle between the stand member and the case. Preferably, the handheld computing device is a system adapted to have a storage configuration, a laying usage configuration, and a tilted usage configuration. The handheld computing device may be a graphing calculator, for example.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: May 9, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Matthew Thomas Nicolosi