Patents Represented by Attorney, Agent or Law Firm J. Matthew Zigmant
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Patent number: 6781445Abstract: Methods and apparatus for buffering RF signals. A method includes receiving an input signal, wherein the input signal alternates between a first polarity and a second polarity. From the input signal, a first current is generated, wherein the first current is proportional to the input signal when the input signal has the first polarity, and approximately equal to zero when the input signal has the second polarity, and a second current is generated, wherein the second current is proportional to the input signal when the input signal has the second polarity, and approximately equal to zero when the input signal has the first polarity. A third current is generated proportional to the first current, and a fourth current is generated proportional to the second current. The first and fourth currents are applied to a first terminal of an inductor; and the second and third currents are applied to a second terminal of the inductor.Type: GrantFiled: April 13, 2001Date of Patent: August 24, 2004Assignee: Zeevo, Inc.Inventor: Arnold R. Feldman
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Patent number: 6759871Abstract: Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.Type: GrantFiled: April 22, 2003Date of Patent: July 6, 2004Assignee: Altera CorporationInventors: Triet Nguyen, Changsong Zhang, David Jefferson
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Patent number: 6750715Abstract: Methods and apparatus of amplifying signals. One method includes receiving a variable power supply, generating a variable bias current, and applying the bias current to a load such that an average output voltage is generated. The method further includes receiving an input signal, generating a current proportional to the input signal, and subtracting the current from the variable bias current. As the variable power supply changes value by a first amount, the variable bias current is varied such that the average output voltage varies by the first amount.Type: GrantFiled: April 16, 2001Date of Patent: June 15, 2004Assignee: Zeevo, Inc.Inventors: Stephen Allott, Iain Butler
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Patent number: 6747903Abstract: Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.Type: GrantFiled: January 14, 2002Date of Patent: June 8, 2004Assignee: Altera CorporationInventors: Philip Y. Pan, Chiakang Sung, Joseph Huang, Bonnie Wang, Khai Nguyen, Xiaobao Wang, Gopinath Rangan, In Whan Kim, Yan Chong, Tzung-Chin Chang
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Patent number: 6629188Abstract: A cache memory apparatus for graphics and other systems. The cache memory apparatus includes a cache memory having a first number of cache lines, each cache line addressable by a cache line address; a first plurality of storage elements coupled to a first address bus; and a second plurality of storage elements coupled to the first plurality of storage elements. The first plurality of storage elements holds a second number of cache line addresses, and the second plurality of storage elements holds a third number of cache line addresses.Type: GrantFiled: November 13, 2000Date of Patent: September 30, 2003Assignee: Nvidia CorporationInventors: Alexander L. Minkin, Oren Rubinstein
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Patent number: 6600337Abstract: Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.Type: GrantFiled: April 26, 2001Date of Patent: July 29, 2003Assignee: Altera CorporationInventors: Triet Nguyen, Changsong Zhang, David Jefferson
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Patent number: 6529428Abstract: A method and apparatus for testing memory devices. One embodiment provides a method including receiving a first input data bit having a first polarity, and receiving a second input data bit having a second polarity, wherein the second polarity is the complement of the first polarity. The method also includes writing the first input data bit to a first portion of a plurality of memory cells, writing the second input data bit to a second portion of a plurality of memory cells, and reading data bits from the first and second portions of the plurality of memory cells. An active signal is generated if the data bits read from the first portion of the plurality of memory cells and complements of the data bits read from the second portion of the plurality of memory cells each have the same polarity.Type: GrantFiled: May 22, 2001Date of Patent: March 4, 2003Assignee: G-Link TechnologyInventor: Jong-Hoon Oh