Abstract: A linear phase FIR filter includes a multiplication/accumulator engine which is operable to receive the multi-level data stream and multiply it by predetermined filter coefficients. The coefficients are symmetrical to allow a pre-addition operation wherein the data is first stored in a buffer and then the data for symmetrical coefficients added before multiplication by the coefficient. This results in a reduction of multiplications by a factor of two, thus allowing the multiplication/accumulator engine to operate at one-half the clock rate of the oversampled multi-level data bit stream.

Abstract: An electronic circuit having a circuit stage, such as a switched capacitor stage or a 1-bit digital-to-analog converter and switched capacitor filter, that is loaded with a load impedance employs current feedforward to substantially cancel effects of the load impedance. A circuit includes a circuit stage and a load impedance following and connected to the circuit stage. A current feedforward circuit is connected to the load impedance, substantially cancelling the load impedance to improve linearity of the digital-to-analog converter or switched capacitor filter.

Abstract: A double-talk detector for an echo canceller includes power estimators (60) and (62) which are utilized to measure the ERLE value in a calculator (64). This ERLE is stored in a register (70) when it is the largest value generated. This register (70) is updated whenever a new and better ERLE occurs. A fraction of the value in register (70) is utilized as an input to a comparator (88), and then compared to the current ERIE value. If the current ERLE differs from the SERLE in register (70) an inhibit signal is generated for blocking the updates of an adaptive filter (40). The value stored in the register (70) is periodically decremented to reduce the value thereof. This decrement operation is performed in response to detection of an utterance from the far-end. A half-Duplex operation is provided with two attentuators (352) and (354) to provide a switching operation and allow only one side access to the communication path.

Abstract: A data communication circuit of a computer system, includes transmitter and receiver circuits each having first and second data paths for respectively communicating synchronously and asynchronously formatted data on an alternatively selected basis, and a control circuit for controlling such communications. Included in the first data paths of the transmitter and receiver circuits are certain field check generating or error checking circuitry which are switchably coupled by their respective control circuits to their corresponding second data paths when synchronously formatted data is being asynchronously communicated through the second data paths.

Abstract: A method and apparatus for monitoring and controlling power to a device such as a PCMCIA/PC card. A PCMCIA/PC card adapter is provided for communicating data and control signals to and from a PCMCIA/PC card and a host processor. The PCMCIA/PC card adapter may communicate with the PCMCIA/PC card to determine the correct voltage(s) for the PCMCIA/PC card. The PCMCIA/PC card may then communicate instruct a power control circuit to provide an appropriate voltage to the PCMCIA/PC card. The power control circuit may be provided with status monitoring registers containing status data reflecting monitored conditions of the PCMCIA/PC card and power supply. A System Management Bus (SMB) may link the power control circuit and the PCMCIA/PC card adapter. If an abnormal status is detected in the PCMCIA/PC card or power supply (e.g.

Abstract: An output driver is provided for operating in a primary power supply environment to drive an output system that can have voltages associated therewith that are higher than the primary power supply level. The driver includes a pull-down N-channel (34) and a pull-up P-channel transistor (44). An output node (40) is driven by the transistor (34) and (44). An N-channel protection device (38) is disposed between node (40) and transistor (34) and an N-channel transistor (48) is disposed between node (40) and transistor (44). Transistor (38) has the gate thereof biased to the primary supply voltage level and the transistor (48) has the gate thereof biased to a voltage slightly above the primary supply voltage level.

Abstract: A synchronous serial communication link between a controller and a peripheral is resynchronized by the sending of a series of bits at a first logic level by the controller. The series of bits is long enough to ensure that the peripheral will decode a command word in which all of the bits are at the first logic level. The peripheral, upon decoding such a command word, resets the synchronization circuitry within the peripheral. The controller then sends a single bit of the opposite logic state followed by serial data. The peripheral, upon receipt of this bit of the opposite logic state, releases the synchronization circuitry from its reset condition and begins to decode the serial data in synchronization with the controller.

Abstract: A very high gain cascode amplifier includes a cascoded differential structure wherein a cascoded N-channel leg comprised of two series connected transistors (56) and (58) are connected between an output node (30) and ground with a corresponding P-channel cascode leg comprised of series connected P-channel transistors (38) and (40) connected between node (30) and V.sub.DD. Transistor (58) is connected to bias voltage, with transistor (56) having a gate thereof connected to a bias circuit (72) which provides gain thereto to increase the gain of a cascoded leg while not introducing any error into the amplifier. The bias circuit (72) has an imbedded structure that sets the gate voltage of transistor (56) to a voltage equal to one threshold voltage plus twice the V.sub.on voltage of transistors (56) and (58).

Abstract: A host adapter of a computer system includes combinational logic circuit eliminating both positive and negative-glitches from an input signal. The circuit comprises two NAND gates and two delay elements in one embodiment. The delay introduced by second delay element is twice that of the first delay element. The first delay element receives as input the input signal. The first NAND gate receives as inputs the input signal and the output of the first delay element. The second delay element receives as input the output of the first NAND gate. The second NAND gate receives as inputs the output of the first NAND gate and the output of the second delay element. The output of the second NAND gate comprises the input signal with both positive and negative glitches having a duration of less than the delay of the first delay element eliminated. In a second embodiment, the two NAND gates are replaced by two NOR gates.

Abstract: A variable sample rate approximation technique is used for coding and recreating musical signals in a wavetable synthesizer. Many sounds inherently include one large fast transfer of energy followed by vibrations that dampen over time so that the bandwidth requirement of a musical sound is reduced with passing time. Using the variable sample rate approximation technique, musical sounds are classified into two categories, sustaining sounds and percussive sounds. A sustaining instrument creates a noisy stimulus then sustains the sound created by the noisy stimulus. A percussive instrument is also a noisy source and generates a sound signal having high frequencies that decay rapidly while sustaining instruments sustain at all frequencies nearly equally. The sustaining and percussive instruments have substantially different waveform characteristics but present similar conditions with respect to memory reduction.

Abstract: A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplier. This input circuitry includes a plurality of Booth recoding logic cells that provide the control signals to multiplexers in the adder cells in the array. The Booth recoding logic cells receive different subsets of bits of the second number and generate the Booth recoded control signals as a function of the received subset of bits. Each Booth recoding logic cell includes balanced logic circuitry for generating all of the Booth recoded control signals from that Booth recoding logic cell at the same time. The balanced logic circuitry minimizes temporary short-circuit paths in the multiplexers in the adder cells. The input circuitry also includes a split bus that provides the first number to the array.

Abstract: An apparatus and method for efficiently receiving a long string of short data packets. Storing a long string of short data packets received from external devices can be inefficient in terms of system resources such as system memory and CPU time. In the preferred embodiment of the present invention, both the number of data packets in the FIFO buffer and the demand of system memory are monitored. A FIFO buffer of at least 32 bytes deep and having a packet-based threshold is implemented to monitor the number of data packets in the FIFO buffer. When the number of data packets in the FIFO buffer is equal to or exceeds the threshold and there is a predetermined number of free buffer memory available, data is transferred from the FIFO buffer to system memory. The number of data packets transferred from the FIFO buffer is also monitored to control the amount of data transfer. Any data stuck inside the FIFO buffer for a predetermined period of time is automatically unloaded.

Abstract: A method and apparatus for using multiple code rates for forward error correction in a cellular digital data radio communication system. Each base station broadcasts a quantity called the power product (PP), which is equal to the base station transmit power, P.sub.BT, multiplied by the power level received at the base station, P.sub.BR. For a mobile unit to determine its appropriate transmit power, P.sub.MT, requires measuring the power received, P.sub.MR, at the mobile unit and performing the following calculation: P.sub.MT ==PP/P.sub.MR. When channel path loss is large, it is possible that the power control calculation will return a value greater than the maximum transmit power capability of the mobile unit. In such a case, the mobile unit selects a lower code rate. Base station receiver sensitivity improves as the code rate decreases, so the result is similar to increasing the transmitter power. In the preferred embodiment, the invention uses 3 different code rates.

Abstract: A 1-bit discrete time digital-to-analog converter which samples a reference voltage and ground potential onto two charging capacitors during a sample phase of each sampling period, and which transfers the charge on one of the capacitors, as determined by a digital input signal, onto an integrator during a transfer phase of said sampling circuit, draws current from the reference voltages which is independent of the data into the converter. The improvement comprises the addition of at least one phase to each sampling period so that the current drawn from said reference voltage is essentially independent of said digital input signal.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable.

Abstract: A method and arrangement for controlling input/output (I/O) operations in a computer system provides multiple PC card controllers but allows legacy software to be used. A PCI bus is coupled to a central processing unit, and an ISA bus is coupled to the PCI bus by a bridge. At least one PC card controller is coupled to the PCI bus and at least one other PC card controller is coupled to the ISA bus. Each PC card controller has at least one socket in which a device is connectable, each socket being separately addressable by the processor at an (I/O) address through the respect PC card controller. Each controller also has a socket pointer register, each socket pointer register being loadable with socket pointer information that uniquely identifies each socket of the controller among all of the sockets of the plurality of controllers in the computer system. Each controller also has an index register and a plurality of data registers, the index stored in the index register pointing to one of the data registers.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: An analog modulator is provided having seven switched-capacitor integrators (62)-(74) disposed in a leap-frog filter configuration with a plurality of feedback taps (76)-(88) provided from the output to each of the integrators (62)-(74). These are summed in a summation junction (90), the output thereof input to a quantizing circuit (92) for input back to a summation junction alter a D to A circuit (60) for summation with the analog input signal and then input to the first integrator (62). The first feedback structures (98)-(102) are provided for connection between the output of the last of the integrated structures (74) and the input of the preceding one thereof such that the feedback structure (98) is connected across integrators (64) and integrator (66), feedback structure (100) connected between integrators (68)-(70) and integrator (102) connected against integrators (72) and (74).

Abstract: Disclosed herein are methods and apparatus for detecting the presence of a CDPD carrier in a channel of a cellular system (although the invention is broadly applicable to detecting a specific kind of carrier associated with an "overlay" system, wherein an "overlay" system is one that shares the frequency allocation of another system on a non-cooperating basis). This specification describes a spectral estimation technique for detection of a CDPD carrier. In addition, this specification describes an MMSE (minimum mean-squared error) method that improves on the spectral estimation method.