Abstract: A digital display tape measuring device is disclosed having a display screen exteriorly for displaying the measured distance. A tape having electrical conductivity capabilities and an insulator disposed longitudinally along the tape dividing the tape into two electrical conductors, and having a tip thereof electrically connecting both of the electrical conductors together such that an electrical circuit is formed with resistance that varies as the tape is extracted from device. An ohmmeter electrically coupled across the electrical circuit for measuring the circuit resistance. A microprocessor having inputs thereof coupled to outputs of the ohmmeter and having outputs coupled to said display screen. The microprocessor computes measurements made by as a function of the resistance measured by the ohmmeter.

Abstract: A dynamic re-programmable logic array is disclosed which has an AND array disposed for receiving n input signals, an OR array providing k output signals on k output lines and m term lines and m bit lines coupling the AND and OR arrays, wherein the array comprises new and improved random access AND and OR arrays incorporating programmable charge storage elements. Refresh logic is also provided for periodically restoring the charge programmed on the charge storage elements.

Abstract: An aerodynamically enhanced heat sink is disclosed, which heat sink includes a plurality of metallic pins each having one end thereof affixed to the integrated circuit package and the second end thereof being disposed for heat dissipation. The plurality of pins are made of varying lengths such that a partial hemisphere is formed with the second ends thereof.

Abstract: An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.

Abstract: A new and improved content addressable memory cell is disclosed, which cell stores data supplied on a load data input terminal thereof. The disclosed memory cell is adapted for comparing data supplied on a compare data input terminal thereof with data stored in the cell, and for supplying an output signal on a match data output terminal when the compare data is the same as the data stored in the cell. A latch circuit is employed as the storage element of the cell. First and second means are each coupled between a reference potential and the match data output terminal, which means are operative in response to the state of the latch circuit and the compare data supplied on the compare data input terminal.

Abstract: A re-programmable logic array is disclosed which has an AND array disposed for receiving n input signals on n rows of m cells per row, and an OR array providing k output lines on k rows of m cells per row. The AND and OR arrays are coupled together by m term lines. Each of the rows of the AND and OR arrays include shift register means of m charge storage elements having an input terminal coupled to the first of the m charge storage elements and an output terminal coupled to the mth one of the m charge storage elements. Multiplexors are coupled to each of the rows of both the AND and OR arrays to select between a programming operation and a recirculating refresh operation.

Abstract: A new and improved shifter circuit for multiplexing bytes of data into various orders on a finite size bus is disclosed. The improved shifter circuit includes an array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each shifter circuit has P data input terminals and P output terminals. The letters N, M and P represent integers. Each of the P output terminals of each of the M shifter circuits in a group are coupled to one another, respectively, so as to form N.times.P output terminals of the array.

Abstract: This disclosure relates to a programmable logic array having an AND array disposed for receiving n input signals, an OR array providing k output signals on k output lines and m term lines coupling the AND and OR arrays together. New and improved AND and OR arrays are disclosed wherein the AND array includes n X m cells and each cell has first and second transistor means coupled in series between one of the term lines and a reference potential. Each cell includes a storage element that has an output terminal coupled to the control element of the first transistor means and one of the n input terminals is coupled to the control element of the second transistor means. The OR array includes m X k cells wherein each cell has third and fourth transistor means coupled in series between one of said output lines and a reference potential.

Abstract: A method of attaching semiconductor die to a package substrate and a composition for such die attach is disclosed, which method and composition comprise the combination of a low and a high-melting powder with a vehicle consisting of a solvent and a binder so as to form a thick-film ink. The ink is deposited onto the package substrate and the semiconductor die with a metallized back surface is located in contact with the deposited ink. The package containing the ink and the die is heated to a temperature of approximately 160.degree. C. so as to remove the solvent from the powders and the residual binder. Next, the package is fired at a temperature within the range of approximately 200.degree. C. to 430.degree. C. so as to melt the low-melting powder which bonds the chip to the package substrate. Then, a lid is sealed over the die-receiving cavity of the package by heating the package and the bonded die to a temperature within a range of approximately 400.degree. C. to 450.degree. C.

Abstract: This disclosure relates to a variable pulsewidth gated clock generator which is able to provide output clock signals with the same rise rate as an external driving clock with the output signal being varied in duration according to logic conditions within the integrated circuit. The circuit of the present invention as disclosed includes a latch which is set by the first phase of a two-phase clock to set the internal logic of the circuit to generate a large output signal during the second phase of the two-phase clock.

Abstract: This disclosure relates to circuitry which includes a low threshold detector and a high threshold detector in the form of inverters the respective output signals of which are combined in such a manner that the output signal of the circuitry is a function of the input signal rising above a low threshold and remaining in an on condition until the input signal has risen above a high threshold and then declined below it. In addition, the circuitry includes a circuit memory element in which is stored the last stable state of the circuitry so that if noise or transients should occur on the input line, the circuitry can return to that stable state. This circuit enables the rapid detection of a memory readout even though the signals on the memory sense lines have relatively slow rise and fall times due to the capacitances on those lines which in turn are due to the large number of memory cells involved. Furthermore, the disclosed invention can be employed in any system in which switching speed is of importance.

Abstract: Disclosed is a digital computer that includes a memory means in which each of the instructions that the computer executes is represented by first, second, and third sets of microcommands. For any one particular instruction, the first set of microcommands is executed before the second set and the second set is executed before the third set. But the computer also includes a control means which directs the execution of the microcommand sets such that between the execution of the first and second microcommand sets for one instruction there is executed the third microcommand set for a prior instruction, and between the execution of the second and third microcommand sets for that same one instruction there is executed the first microcommand set for a subsequent instruction.

Abstract: This disclosure relates to a system and method for the synchronization of variable-length messages being transmitted between stations of a local area contention network where the messages are made up of a variable number of fixed-length packets. This system is adapted for automatic address assignment of different stations of the network so that the network may be expanded or contracted by adding stations and removing stations respectively. In this manner, a very reliable network is provided in that the failure of any particular station does not interfere with the functioning of the other stations in the network or the network itself. In addition, the system includes provision for associating various server stations with a given procedure so that a client station may broadcast a request for a procedure and corresponding server stations will send the response to the client station containing the network identification of the server station.

Abstract: In the disclosed read-only memory, address decode means for addressing information in the memory lie in a semiconductor substrate; an insulating layer covers the address decode means; an array of spaced-apart metal lines and semiconductor lines lies on the insulating layer over the address decode means; outputs from the address decode means respectively couple through the insulating layer to the metal lines and to the semiconductor lines; and a plurality of mask selectable electrical contacts between the metal lines and semiconductor lines forms a matrix of mask selectable diodes over the insulating layer representative of the information in the memory.

Abstract: This disclosure relates to a system and method for the synchronization of variable-length messages being transmitted between stations of a local area contention network where the messages are made up of a variable number of fixed-length packets. This system is adapted for automatic address assignment of different stations of the network so that the network may be expanded or contracted by adding stations and removing stations respectively. In this manner, a very reliable network is provided in that the failure of any particular station does not interfere with the functioning of the other stations in the network or the network itself. In addition, the system includes provision for associating various server stations with a given procedure so that a client station may broadcast a request for a procedure and corresponding server stations will send the response to the client station containing the network identification of the server station.

Abstract: An interconnection circuitry for two local area contention networks which is adapted to jam the respective networks when stations on both sides of the interconnection circuitry attempt transmission. If stations on opposite sides of the interconnect circuitry begin transmitting at the same time, the interconnect circuitry operates to place a high signal on the channel of each network and all stations will detect that the data is garbled and discard it.

Abstract: This disclosure relates to a system and method for the synchronization of variable-length messages being transmitted between stations of a local area contention network where the messages are made up of a variable number of fixed-length packets. This system is adapted for automatic address assignment of different stations of the network so that the network may be expanded or contracted by adding stations and removing stations respectively. In this manner, a very reliable network is provided in that the failure of any particular station does not interfere with the functioning of the other stations in the network or the network itself. In addition, the system includes provision for associating various server stations with a given procedure so that a client station may be broadcast a request for a procedure and corresponding server stations will send the response to the client station containing the network identification of the server stations.

Abstract: Disclosed is a programmable multiplexer integrated on a semiconductor chip comprised of a plurality of fixed multiplexer circuits, each of which includes a plurality of data inputs, a plurality of control inputs, and an output for passing a signal from any one of the data inputs to the output in a fixed predetermined fashion in response to encoded signals on the control inputs; and associated with each of the fixed multiplexer circuits is a programmable memory for generating the encoded control signals by performing respective programmable transformation of one common address that is sent to all of the memories.

Abstract: This disclosure relates to a network of stations having a single transmission bus. A bus assignment control line is daisy-chained to all of the stations to form a closed loop such that an assignment signal will circulate through the loop and return to the originating station after each station has been given an equal chance to be serviced. Stations of a lower priority can be attached to the bus in such a manner that the preceding station will direct the bus assignment control signal to the lower priority stations with a frequency less than the transmission of the assignment control signal to a succeeding higher priority station.

Abstract: Disclosed is an interferometer having an optical flat having a coated reference surface of aluminum whose thickness is in the range of 100-500 A (preferably about 300 A) covered with a coating of silicon dioxide of a thickness in the range of 1,000-10,000 A (preferably about 3,000 A). Such a coating on an optical flat when in engagement with a surface of an object to be tested greatly enhances the contrast of the interference fringes.