Abstract: A circuit and method for a display controller especially adapted for display memories organized in arrays. The invention permits high speed modification of the contents of a display by generating the address signals of a selected linear pattern as the data block to be modified is retrieved from the display memory. For vectors, the addresses are generated in the same time as required for data block retrieval. The invention also permits calculation of the addresses of simple curves as the data block to be modified is retrieved, though calculation times typically are longer than for vectors. Modified Breshenham's algorithm is used for the address calculation.

Abstract: A folding-type A/D converter for converting an analog input signal to an n-bit digital code, the A/D converter having a transfer function dividing the analog input signal into at least n-1 segments, each such n-1 segment having an amplitude level corresponding to the significance of a given bit of the digital code and having linear parts which are mirror images of one another extending over 2.sup.n transition levels L. The A/D converter includes voltage-current converters for converting voltage input signals to current signals, a plurality of circuit stages for producing the linear parts in the current domain in response to the current signals, and a converter for converting the linear parts to a logic 1 or logic 0 of the bits of the digital code.

Abstract: The invention comprises an improved integrated circuit structure wherein an active device is formed in a silicon substrate for forming an intrinsic base region over a buried collector and an emitter is formed on the intrinsic base region to comprise three electrodes of the active device and at least one extrinsic base segment is formed in the substrate adjacent to the intrinsic base region to provide a contact for the intrinsic base; the improvement which comprises: separating the extrinsic base segment from the emitter formed on the intrinsic base to prevent the formation of a parasitic P-N junction between the extrinsic base and the emitter.

Abstract: The invention discloses an improved PC board package for one or more integrated circuit dies comprising a plurality of PC boards bonded together to form a composite. The composite has at least one cavity, for mounting of an integrated circuit die, formed in at least one PC board of the composite. The cavity walls are plated to seal off portions of the PC board exposed by formation of the cavity to thereby prevent subsequent outgassing. Heat pipes are formed in a PC board adjacent the PC board with the cavity to conduct heat from an integrated circuit chip mounted in the cavity to an opposite surface of the package.

Abstract: An improved process is disclosed for making an integrated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning silicon dioxide and silicon nitride layer on a layer of silicon. The improvement comprises isotropically etching the silicon layer to provide an enlarged shallow etch area undercutting the patterned silicon dioxide and silicon nitride layers. Subsequent deeper anisotropic etching to form the trench will result in a trench having an enlarged upper width which, in turn, prevents the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps. Possible creation of openings to such voids in the polysilicon during subsequent planarization is thereby eliminated thus avoiding undesirable oxidation of such voids and undesirable stress formation therefrom.

Abstract: A circuit arrangement for reducing a reference supply voltage level of a reference generator for an ECL circuit during a power-down mode includes a reference generator for producing a reference supply voltage. A first switching network is connected to the input of the reference generator for disabling of the input of the reference generator in response to a control signal so as to reduce the level of the reference supply voltage. A second switching network is connected to the output of the referenced generator for disabling of the output of the reference generator in response to the control signal.

Abstract: A CPU data path portion having an ALU, an adjuster unit, a shifter unit and a shift register unit is disclosed. The CPU is capable of selectively forming the sum or difference of a first BCD operand and a second BCD operand by arithmetically combining the operands with the ALU to form binary results, the results dependent upon the arithmetic operation selected and adjusting the results with the adjuster unit into BCD, the adjustment also dependent upon the arithmetic operation selected. The CPU is further capable of selectively converting an operand from binary to BCD format or from BCD to binary format by iteratively shifting the operand between the shifter unit and the shift register unit and correcting the operand with the ALU, the direction of the shift and the ALU correction dependent upon the conversion selected.

Abstract: An improved ECL circuit in which reference voltages have been eliminated is provided. The base of the reference switching transistor which is usually connected to a reference voltage is instead connected to the emitter of an emitter follower transistor coupled to the input switching transistor. The need for a reference voltage is thus eliminated because the emitter of such emitter follower transistor, and thus the base of the reference switching transistor, will be at the opposite level of the input to the base of the input switching transistor.

Abstract: A combination circuit formed of a functional portion circuit coupled to a latch or flip-flop circuit portion which is fabricated as a single gate on an integrated circuit semiconductor chip. The functional circuit portion can be a multiplexer, or other logic functions such as AND, NAND, OR, NOR, XOR, etc. A special buffer circuit is provided which generates a latch enable signal for the latch or a clock signal for the flip-flop in the combination circuit. The latch enable signal or the clock signal for the combination circuit has to override the high level values of the normal second level ECL signals while their low level values can be the same as those of normal second level ECL signals. This combination circuit has the advantage of higher speed, lower power consumption, and reduced component counts which is favorable for integrated circuits.

Abstract: A phase detector for detecting in real time the difference in phase between frequency pulse signals and data pulse signals, including a control signal generator for generating control signals corresponding to the occurrence of the frequency pulse signals and the occurrence or non-occurrence of the data pulse signals, and a circuit, operative during the occurrence or non-occurrence of the data pulse signals, for producing a phase error signal indicating differences between the real time occurrence of the frequency pulse signals and the data pulse signals. Another circuit of the phase detector, if needed, responds to the control signals to correct the integral of the phase error signal.

Abstract: An improved ECL gate having faster output transition times without requiring additional current is provided. Two switching transistors have their emitter terminals connected to a first current source. A reference switching transistor has its base connected to a reference voltage and an input switching transistor has its base connected to an input terminal. An emitter follower transistor is coupled to each switching transistor. A second current source is connected to each of the emitter follower transistors by coupling circuitry which shunts current from one emitter follower to the other thereby increasing the transition speed of the outputs. In the preferred embodiment, the emitters of the current source transistors for the two outputs are coupled through a common resistance to ground. The collector of the inverting emitter-coupled transistor is coupled via a capacitor to the base of the current source transistor for the non-inverting output.

Abstract: An improved method for planarizing an isolation slot, having its walls previously oxidized, is disclosed which comprises depositing a first layer of a material; etching the first layer back to a predetermined depth below a reference point; depositing a second layer of an oxidizable material on the surface of the first layer; etching the second layer; and then oxidizing the second layer of oxidizable material. Formulas are disclosed for calculating the minimum and maximum depths of the etch back of the second layer and the minimum depth of the etch back of the first layer given the width of the slot and the thickness of the oxide layer to be grown in the surface of the second layer to thereby insure that any voids, microcracks, or discontinuities formed in the second layer are removed by the etch and that the oxide subsequently grown in the surface of the second layer does not penetrate down to the surface of the first layer and any voids, microcracks, or discontinuities therein.

Abstract: A plurality of locally-distributed ECL slave reference generators positioned throughout a large monolithic integrated circuit device for tracking closely a central master reference generator to provide stable slave reference voltages wherein each of the slave reference generators includes a differential comparator which has first and second inputs coupled to a master reference voltage and a slave reference voltage respectively for comparing the master reference voltage and the slave reference voltage and for generating a difference voltage output. A constant current source is coupled to the differential comparator for establishing a constant current flow through the differential comparator. A negative feedback device is responsive to the difference voltage output for supplying a feedback to the second input of the differential comparator as that the slave reference voltage tracks closely the master reference voltage.

Abstract: Disclosed is a digital signal translation circuit for translating a first type signal to a second type signal which comprises a master latch and a slave latch. The master latch latches the incoming first type signal during a first portion of the clock signal. A slave latch latches the master latch output and generates a differential output. The differential output of the slave drives an output driver circuit which generates the second type signal.

Abstract: A clock driver circuit for low level gates having high fanout capabilities includes a first circuit portion, a second circuit portion, an output transistor and a load resistor. The first circuit portion is formed of a first NAND logic gate and a first inverter gate. The input node of the first inverter circuit gate is coupled to the output node of the first NAND gate. The input node of the first NAND gate is connected to an input circuit terminal. The second circuit portion is formed of a second NAND logic gate, a third NAND logic gate and a second inverter gate. The input nodes of the second and third NAND gates are coupled together and to the input circuit terminal. The output node of the second and third NAND gates are coupled together and to the input node of the second inverter gate. The output node of the second inverter gate is connected to an output circuit terminal.

Abstract: A single-array memory employs a novel storage cell providing dual read/write access via either an "A"-side or a "B"-side. The storage cell uses a unique circuit in which read current is borrowed during writing into the cell. Asymmetrical read/write delay circuitry is provided to avoid overwriting the contents of a storage cell during the read-to-write transition. Row-selection decoders use Schottky-clamping diodes in a way which provide an equivalent oscillation-damping capacitance at the base of the selected-row driver transistor. The single-array memory can be advantageously used as part of a single-chip VLSI four-port register file permitting simultaneous reading and/or writing of registers from any of two read ports or two write ports, respectively. Unidirectional busses connect each storage cell to each of the four ports.

Abstract: A method is presented for fabricating a bipolar semiconductor device utilizing a combination of junction isolation, oxide isolation, stepper lithography and plasma etching to produce an integrated circuit device having reduced device sizes and increased performance. The method includes the steps of removing portions of a masking layer to expose surface areas of an epitaxial layer, where first type isolation regions are then formed; then forming second type isolation regions in the epitaxial layer, and forming base, emitter and collector contact regions, also in the epitaxial layer; and forming conductive lines on the base, emitter and collector contact regions.

Abstract: An improved logic level translator circuit for translating logic signals of non-TTL circuits to logic signals of TTL circuits is presented. The translator circuit as presented includes circuitry for providing elimination of noise spiking and the resultant erroneous switching caused by simultaneous conduction of TTL circuit outputs as they change states.

Abstract: The invention comprises an improved isolation slot in an integrated circuit structure which minimizes damage to the silicon substrate. The improved isolation slot is formed by etching a slot in the substrate of an integrated circuit structure; depositing a buffer layer in the slot adjacent the walls of the slot; and forming an isolation oxide layer in the slot over the buffer layer; whereby the presence of the buffer layer between the substrate and the isolation oxide minimizes damage to the substrate by the oxide. In a preferred embodiment, the buffer layer comprises polysilicon which is partially oxidized to form the isolation oxide layer. A barrier layer is formed between the slot walls and the polysilicon buffer layer to electrically insulate the polysilicon from the adjoining integrated circuit structure.

Abstract: An apparatus and a method for character and graphics pattern generation in a bit mapped graphics display system is disclosed that includes a pixel data manager 14 for supplying character bit maps and graphics patterns to a visible display memory 22. A character information memory 24 is utilized for the storage of character descriptive information which includes an address table 26, macro-instructions 28, 30, and 32, and character bit maps 34, 36, and 38. Each character in a set of characters has an associated macro-instruction and character bit map. The address table contains memory addresses that point to the macro-instructions. Each macro-instruction contains executable instructions that establish the size and location of a corresponding character bit map. To supply a character to the visible display memory, the pixel data manager fetches and executes a corresponding macro-instruction. Overhead burden on the central processing unit is minimized.