Abstract: At least two direct access storage devices (DASDs), which are predetermined to record the same data from a central processing unit (CPU), are normally kept synchronzied with each other except during the power up phase. The DASD synchronization is controlled and maintained by synchronization control means independent of any commands from the CPU. When one or more commands such as SEEK and SET SECTOR or LOCATE commands are transferred from the CPU to a control unit over a single data transfer path between them, desired identical records on the synchronized DASDs are concurrently located while the DASDs are disconnected from the data transfer path. Upon locating the desired identical records, the DASDs are reconnected to the data transfer path. Then, a WRITE command is transferred from the CPU to the control unit for concurrently recording the same data onto the synchronized DASDs at the desired record locations.

Abstract: A method for removing hidden lines in a two-dimensional surface chart disclosing an image of a three-dimensional surface, includes storing the X, Y and Z co-ordinates of selected points (A, B, C, D, E) of the surface as a first matrix, transforming the first matrix into a second matrix indicating the drawing sequence through the selected points, rotating the points of the second matrix around the Z-axis a first angle .alpha., rotating the second matrix points a second angle .beta. and drawing the two-dimensional surface chart in accordance with the indicated sequence using the X and Y co-ordinate values of the rotated points. The drawing sequence comprises a drawing operation of X-traces, an X-trace being defined as a line passing through points having substantially the same Y values in the first matrix, the drawing operation of one X-trace being followed by a plurality of .DELTA.

Abstract: The elimination of crosstalk between data lines and pixel cells in a thin film transistor/liquid crystal display is accomplished by applying a data signal to a given data line for a time period less than the standard scan line period of the display, and applying a crosstalk compensation signal to the given data line for the remainder of the scan line period.

Abstract: Speaker adaptation which enables a person to use a Hidden Markov model type recognizer previously trained by another person or persons. During initial training, parameters of Markov models are calculated iteratively by, for example, using the Forward-Backward algorithm. Adapting the recognizer to a new speaker involves (a) storing and utilizing intermediate results or probabilistic frequencies of a last iteration of training parameters, and (b) calculating new parameters by computing a weighted sum of the probabilistic frequencies stored during training and frequencies obtained from adaptation data derived from known utterances of words made by the new speaker.

Abstract: A switching apparatus and adjustable time delay protocol to provide switching between N processor system devices in which each device is connected via N+S fibers to N+S switching planes, with one fiber being used for the connection from a device to one of the N+S switching planes. N fibers provide the desired bandwidth and S fibers are used as standby fibers in the event of failure of any of the N fibers. An additional C fiber from each device to a single matrix controller are used to provide control information. The single controller provides control for all N+S switching planes. Each switching plane converts the optical signals that are received over M fibers to electrical signals. The electrical signals are then switched and converted to optical signals by the respective switching planes. Thus, each of the optical signals received over each of the M fibers are transmitted to a respective other one of the M fibers.

Abstract: A method of reducing the number of connections in, and increasing the testability of, a logic network. This is accomplished by propagating global controlling information through a graphical representation of the logic network. Logically redundant connections are detected and removed by means of this information.

Abstract: A method and apparatus is provided for associating in cache directories the Control Domain Identifications (CDIDs) of software covered by each cache line. Through the use of such provision and/or the addition of Identifications of users actively using lines, cache coherence of certain data is controlled without performing conventional Cross-Interrogates (XIs), if the accesses to such objects are properly synchronized with locking type concurrency controls. Software protocols to caches are provided for the resource kernel to control the flushing of released cache lines. The parameters of these protocols are high level Domain Identifications and Task Identifications.

Abstract: A data processing system includes multiple floating point arithmetic units, for example, an adder and a multiplier. Two putaway busses and two bypass busses are connected to a register file and waiting stages, associated with the arithmetic units, respectively. A special source register is included for keeping track of the source of any result on the busses so that the registers may be connected to the appropriate bus on which the result is to appear in accordance with a busy or mark bit set in each register in the file and in the waiting stage. This allows multiple data items to exit the pipes during any cycle. Therefore, two or more results are produced each cycle.

Abstract: An interlaced raster-scanned color cathode ray tube display in which flicker is reduced by temporally off-setting one of the colors (preferably red) so that normally even-field data for that color is displayed in the odd field and normally odd-field data for that color is displayed in the even field. The temporal shift can be either before or during storage of the bit patterns or during or after reading of the bit patterns.The resulting positional shift of one scan line of the temporally shifted color is compensated for by using the static and/or dynamic convergence circuitry.

Abstract: A data-dependent branch table is a mechanism that is sensitive to operands that will be tested in order to determine branch action outcomes. The data dependent branch table operates in conjunction with a branch history table to anticipate those instances where the branch history table will make an erroneous prediction, and corrects the branch history table prior to the time that the actual prediction is made.

Abstract: A method for rapid windowing of display information in computer graphics is disclosed herein. Image display data is maintained in a hierarchical data tree structure. Small numbers of bits of data called summaries are maintained at the nodes of the tree. The large complete data image is divided into units called boxes. These boxes combine to form a master box for a particular window size. By searching the summaries for each box and locating the window within the master box, traversal of an entire subtree may be terminated quickly, proceed on only some of the subtrees, or proceed through to completion. A clipped image is rapidly generated that can be rendered to the viewer.

Abstract: A support for an object of appreciable weight (e.g., for a CRT display) comprises a mount 10 which, in use is located at a reference height. A crank 20 extends from this mount. A boom 12 is pivotally mounted on the mount and extends therefrom to and carries means (not shown) for attaching the intended object which is to be located at an adjustable height with respect to the reference height. A lift lever 26 and a gas strut 30 are carried wholly by the boom. A lift rod 36 is mounted between a position on the crank remote from the mount/boom axis 18 and the lift lever, the latter being pivotally mounted in the boom. The lift rod and the gas strut are connected to the lift lever, but with the strut at a greater separation from the lever's pivot than the rod. The gas strut engages the boom and counteracts the effects of gravity on the loaded support. In addition to the lift mechanism, the support can also incorporate a parallel motion and a tilt mechanism.

Abstract: A method of generating the layout of CMOS cells from a high-level functional description of the cells, as well as generating the particular details of the CMOS device. In particular, the image of the chip is formed having the polysilicon gates of the transistors on the n-side vertically aligned with those of the p-side vertically aligned with those of the p-side to minimize the wiring effort. The interconnections between the source and drains are orthogonal to the gates, and run along one layer of metal.

Abstract: A data processing system includes a multiple floating point arithmetic unit with a putaway and a bypass bus, which includes a new instruction for handling multiple multiply or divide instructions. These instructions are separated by add operations, including passing the results of each multiply/divide operation on a bypass bus to the input of an adder along with the inputs from an accumulate bypass bus which is the output from the adder for an automatic add operation on an accumulate multiply or accumulate divide operation. This allows two floating point results to be produced each cycle, one of which can be accumulated without any intervening control by the central decoder. The accumulation is performed under distributed control of the accumulator logic itself.

Abstract: A branch history table (BHT) is substantially improved by dividing it into two parts: an active area, and a backup area. The active area contains entries for a small number of branches which the processor can encounter in the near future and the backup area contains all other branch entries. Means are provided to bring entries from the backup area into the active area ahead of when the processor will use those entries. When entries are no longer needed they are removed from the active area and put into the backup area if not already there. New entries for the near future are brought in, so that the active area, though small, will almost always contain the branch information needed by the processor.The small size of the active area allows it to be fast and to be optimally located in the processor layout. The backup area can be located outside the critical part of the layout and can therefore be made larger than would be practicable for a standard BHT.

Abstract: Method and apparatus which restricts software, distributed on magnetic media, to use on a single computing machine. The original medium is functionally uncopyable, until it is modified by the execution of a program stored in a tamper proof co-processor which forms a part of the computing machine. The modified software on the original medium may then be copied, but the copy is operable only on the computing machine containing the co-processor that performed the modification.

Abstract: Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned.

Abstract: For designing the layout of a master-slice VLSI chip steps for placing components and for determining the wiring pattern interconnecting them are alternated in an iterative process. The chip area is partitioned into subareas of decreasing size, the set of components is partitioned into subsets which fit to the respective subareas, and after each partitioning step the global wiring is determined for the existing subnets of the whole network. Due to this interrelation of placement and wiring procedures, advantages with respect to total wire length, overflow number of wires, and processing time can be gained.

Abstract: In a digital data processing system including an Instruction Unit, an Execute Unit, and a multilevel Processor Storage System including a cache memory, additional apparatus is included referred to as a Load Control Block Address Unit for implementing a load control block address instruction which permits prefetching of data from main memory into cache simultaneous with execution of a sequence of instructions in a linked list wherein information determining starting address of a next block in the linked list is stored at a location in the current block at a fixed offset from the beginning of the block.

Abstract: A copy-protection scheme is implemented for software which may be stored on a magnetic storage medium such as a disk. The medium is comprised of sections which are divided into subsections, with an original having indicia on at least one subsection of at least one section that is not modifiable by the medium write process, with a copy having no such indicia, or having indicia in a different pattern. A product program may be stored on the medium, and is executable only if the particular medium is an original. A medium test program may also be stored on the particular medium, and is used to test if the medium is an original or a copy. The test program writes the sections with a test pattern which generates a change in the pattern of magnetic domains of the medium, a subsection at a time, with a subsection responding to the test pattern only in the absence of indicia thereon, to form a stored pattern on the given section.