Patents Represented by Attorney James C. Kesterson
  • Patent number: 5821621
    Abstract: An improved method is provided for integrating polymer and other low dielectric constant materials, which may have undesirable physical properties into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. The present invention combines the advantages of SiO.sub.2 with low dielectric constant materials by placing the low dielectric material only between tightly spaced lines. In a preferred embodiment, a low-k material is spun across the surface of the wafer to fill areas between all interconnect lines. The critical areas, or those where the low-k material is to remain are masked off with resist. The low dielectric constant material in non-critical or widely spaced areas is then etched away, leaving the problematic but desirable low-k material in those areas where needed. A layer of dielectric such as SiO.sub.2 can then be applied to fill the remaining areas and provide spacing between metal layers.
    Type: Grant
    Filed: October 10, 1996
    Date of Patent: October 13, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Shin-Puu Jeng
  • Patent number: 5822473
    Abstract: An optical device for sensing properties in an environment such as the presence of a substance or chemical in the zone to be monitored using optical components integrated on a microchip base or substrate. A preferred embodiment introduces a method for fabricating a miniature microchip chemical sensor by integrating a GaAs LED 14 with a polyimide waveguide 48 and a silicon photosensor 16 on the same chip. Light 18 is emitted at the edge of the GaAs LED 14. A portion of the light propagates is detected by a PIN diode 16. A chemical sensitive material 50 is coated on top of a polyimide waveguide 48. When the gas or chemical to which the material is sensitive appears, the light transmitted from the polyimide to air increases, thus the total signal sensed by the photodetector decreases, whereby the change in light signal indicates detection.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: October 13, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Anton Magel, Terrance Gus McDonald, Jau-Yuann Yang, Han-Tzong Yuan
  • Patent number: 5817569
    Abstract: A method of fabricating a monolithic device, preferably a micromechanical device, from a wafer (20) by carefully selecting the composition of two or more layers of photoresist (52,54). The present invention comprises choosing compatible photoresist layers to avoid generating defects in the layers of photoresist which could allow a wet chemical HF acid etch process to damage an underlying micromechanical device. The present invention allows a very strong solution of hydrofluoric acid to be utilized to remove particles and debris after a partial-saw process, and to remove a damaged portion of an underlying CMOS layer (22) at a region (68) proximate a kerf (62). Using an HF solution having a concentration of about 6% is desired. The present invention substantially improves the yield of micromechanical devices.
    Type: Grant
    Filed: May 8, 1997
    Date of Patent: October 6, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Mike Brenner, Timothy J. Hogan, Sean C. O'Brien, Lawrence D. Dyer, Lisa A. T. Lester
  • Patent number: 5816826
    Abstract: A computer (40) has one or more PC Card peripheral slot assemblies (41a, 41b). The peripheral slot assemblies (41a, 41b) have leads (60a, 60b) which connect in a substantially straight line from receptacles on the PCMCIA device (66) to a SMT connector (58) on a circuit board (64). Two PCMCIA peripheral slots (41a, 41b) can be mounted on either side of the circuit board (64) to reduce overall thickness in a notebook computer (40).
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: October 6, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Allen M. Colemen
  • Patent number: 5818095
    Abstract: A semiconductor device with an optically active region which receives light, and has a layer of metal which blocks the light from the substrate. The substrate contains addressing circuitry which can experience current leakage if photocarriers are allowed to form by contact with light. A layer of metal is deposited as an integral part of the device to prevent the light from reaching the substrate.
    Type: Grant
    Filed: August 11, 1992
    Date of Patent: October 6, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey B. Sampsell
  • Patent number: 5818111
    Abstract: An improved method and structure is provided for integrating HSQ and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. The present invention combines the advantages of SiO.sub.2 and low dielectric constant materials by creating a multilayer dielectric stack of alternating layers of low-k materials and traditional dielectrics. A stabilizing layer is inserted between layers of low-k films. Since the thickness of problematic low-k materials remain less than the cracking threshold, many of the problems discussed above are alleviated. The stabilizing prevents the nucleation and propagation of micro cracks. In a preferred embodiment, interconnect lines 14 are first patterned and etched on a substrate 10. A low-k material such as hydrogen silsesquioxane (HSQ) 18 is spun across the surface of the wafer to fill areas between interconnect lines.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: October 6, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Shin-Puu Jeng, Kelly J. Taylor
  • Patent number: 5818743
    Abstract: A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: October 6, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Wai Lee, Toshiyuki Sakuta
  • Patent number: 5819099
    Abstract: A digital data signal voltage converter for converting a first digital data signal that is asserted at a first pair of voltage levels that are considered the inverse of one another, the two voltage levels being a first low voltage level and a first high voltage level, to a second digital data signal that is asserted at a second pair of voltage levels that are considered the inverse of one another, the second pair of voltage levels being a second low voltage level and a second high voltage level, the second high voltage level being higher than the first high voltage level. The voltage converter includes an active pull-up transistor and an active pull-down transistor, along with circuitry for controlling the second high voltage level. Three-state control may be provided to allow use as an input/output terminal.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: October 6, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Kevin M. Ovens
  • Patent number: 5815420
    Abstract: A microprocessor (5) having at least one arithmetic logic unit, or ALU, (42) for operating upon operands of multiple number representation types is disclosed. The ALU (42) includes a binary logical unit (52) for performing logical operations upon operands in a binary representation, and an arithmetic unit (50, 50') for performing arithmetic operations upon operands in a redundant number representation. The redundant number representation is of a type that may be operated upon by adder circuitry such as signed-digit adders or carry-save adders, where carry information need not propagate along the entire operand. A register file (39, 39') is provided, which stores each operand in both the binary form and in the redundant number representation; a valid bit (V) is provided in combination with the binary portion of each entry in the register file (39, 39').
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: September 29, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Donald E. Steiss
  • Patent number: 5815697
    Abstract: A processor embodiment comprises a microprogram memory circuit (12) comprising a number of separately energizable banks (14a, 14b). Each of the number of separately energizable banks is operable to concurrently output at least one microinstruction. The processor further comprises circuitry for forming a microaddress for addressing the microprogram memory. This circuitry includes circuitry (26, 28) for identifying a value of a first bit (A0) and of a second bit (A1), and the microaddress comprises the first bit, the second bit, and a plurality of main bits (20c). Further, the processor includes circuitry for selectively energizing (24, 13a, 13b) a subset of the separately energizable banks in response to the value of the first bit, and the subset is less than the number of separately energizable banks. Still further, the processor includes circuitry (16) for outputting a first set of microinstructions from the subset of the separately energizable banks.
    Type: Grant
    Filed: January 9, 1997
    Date of Patent: September 29, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Patrick W. Bosshart, Jonathan H. Shiell
  • Patent number: 5815026
    Abstract: An integrated circuit voltage multiplier 30 in a semiconductor substrate of a first conductivity type. The multiplier includes a diode 22, having a first voltage VDD applied to a first port thereof, the diode being made of: 1) a first well 12 of a second conductivity type formed in the substrate, being connected to a second voltage VB; 2) a second well 14 of the first conductivity type formed in the first well, having an electrical contact point comprising the first port of the diode; and 3) a third well 16 of the second conductivity type formed in the second well, having an electrical contact point comprising a second port of the diode. The multiplier also includes a capacitor C3, having a first contact thereof connected to the second port of the diode and having a third, pulsed voltage PH1 connected to a second contact of the capacitor.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: September 29, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Giovanni Santin, Giulio Marotta, Michael C. Smayling
  • Patent number: 5815005
    Abstract: In a preferred embodiment there is a logic circuit (230) which includes both a first (231) and second (232) phase dynamic logic circuit, where each such circuit has a one or more dynamic logic stages. Each dynamic logic stage includes a precharge node(231.sub.1PN), a coupling device (231.sub.1PT) which when conducting couples the precharge node to a precharge voltage (V.sub.DD) during a precharge phase, a discharge path (231.sub.1DT) connected to the precharge node which when conducting couples the precharge node to a voltage (ground) different than the precharge voltage during an evaluate phase, and an output for presenting a logic value responsive to a voltage at the precharge node. The logic circuit further includes control circuitry (PHASE 1 and 2 CLOCKS and 234) for controlling at least one (231.sub.4) of the dynamic logic stages as a storing stage, such that the coupling device (231.sub.4PT) and the discharge path (231.sub.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: September 29, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick W. Bosshart
  • Patent number: 5815641
    Abstract: A spatial light modulator based imaging system (30) with improved peak white performance characteristics. The apparent dynamic range of the spatial light modulator (74) is increased by adding light to pixels neighboring a saturated pixel. An apparent bloom effect is created with the pixels neighboring the saturated pixel appearing brighter, to give sunlight reflecting from the surface of a lake, for instance, more sparkle or highlights. Charts or equations are utilized to determine the degree to which pixel brightness is increased for neighboring pixels. The closer a pixel to a saturated pixel, and the greater the saturation of a particular pixel, the greater increase in brightness for neighboring pixels.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: September 29, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen W. Marshall
  • Patent number: 5815220
    Abstract: A digital sampling and separation unit (12) for a television receiver (10) of a composite video signal, such as an NTSC signal, which has a color subcarrier. The video signal is sampled at a frequency selected in accordance with the invention. This frequency provides samples having a definite and repeating phase relationship with the subcarrier signal. (FIG. 4). As a result, phase reference values can be used to convert the samples into correct color difference values.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: September 29, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen W. Marshall
  • Patent number: 5811317
    Abstract: A method for assembly of bare silicon die onto flexible or thin laminate substrates that minimizes substrate and die warpage induced after underfill cure operations and at the same time reduces the cycle time for the assembly process. More specifically, an opposing layer of thermoset component is adhered to a balance plate (metal) or other material with applicable coefficient of thermal expansion "CTE" and modulus of elasticity on the top of the die. The offsetting layer of material causes the die to warp to the other side and as a result the two self opposing warpage effects neutralize themselves.
    Type: Grant
    Filed: August 25, 1995
    Date of Patent: September 22, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Abhay Maheshwari, Sunil Thomas, Chris Thornton
  • Patent number: 5812116
    Abstract: A low profile and light weight keyboard for portable electronic devices, such as notebook computers. In specific embodiments, the present invention provides a low profile keyboard 218 where the keycap engaging members 202 extend unobstructed below the back plate or circuit board 204. The travel of the key below the back plate may be eliminated from the overall stowed keyboard thickness by popping up the keyboard or otherwise extending the keyboard to a deployed position having sufficient thickness to accommodate the travel of the engaging members 212 below the base 204.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: September 22, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Satwinder D. S. Malhi
  • Patent number: 5813028
    Abstract: A method for invalidating a line in a cache block in a cache memory during a cache write operation, wherein the cache block includes two or more lines of data sharing a common tag address. The method involves generating a read miss request with respect to one or more lines in the cache block, including a tag and block address and an invalidation control bit. When the invalidation control bit is on, the invalidation control bit causes the setting of the validity bits, for those lines in the cache block other than the one or more lines for which the read miss request is generated, to invalid. When the invalidation control bit is off, the invalidation control bit prevents the resetting of the validity bits, for those lines in the cache block other than the one or more lines for which the read miss request is generated.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: September 22, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Sanjive Agarwala, Hiep Tran
  • Patent number: 5812303
    Abstract: A system and method for increasing the number of bits available for use in a video display system that includes at least one spatial light modulator. The system uses a wheel (30) of three colors, or a color wheel that is clear, including at least one segment (34) which has a lower intensity region, referred to as a neutral density filter. Alternately, the filter could be a liquid crystal controller to control either light amplitude or color. By using a lower intensity region, the amount of time available to process the least significant bit of the data sample is lengthened, thereby eliminating the constraint on the number of bits available for display.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: September 22, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory J. Hewlett, Vishal Markandey, Gregory S. Pettitt
  • Patent number: 5809142
    Abstract: A system and method in which a transponder (14) is operable to transmit an original user account balance to an interrogator (12), which in turn calculates a revised user account balance and transmits the revised user account balance to the transponder (14). In one embodiment of the invention, the transponder (14) is further operable to transmit a verification user account balance back to the interrogator (12), which then compares verification user account balance to the revised user account balance that was earlier calculated and stored in an interrogator memory.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: September 15, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Dwaine S. Hurta, Francis B. Frazee
  • Patent number: 5808780
    Abstract: A micromechanical optical switch (30). A reflective surface with two angled reflective surfaces (32,34) positioned opposite a micromechanical device (12). The micromechanical device is positioned such that light input along a path (36) to a first (32) of the two angled reflective surfaces is reflected to the micromechanical device. The micromechanical device then reflects the light to the second (34) of the angled surfaces to be output along another path (38a, 38b). The path (38a, 38b) that the second angled surface (34) outputs the light along is selected depending upon the position of the micromechanical device's reflective member (14). The reflective member (14) deflects from at least one hinge (22) to one of several positions. The number of positions available to the reflective member (14) depends upon the voltage applied to the electrodes (27a, 27b, 27c, 27d). The reflective member (14) makes no contact with any other surfaces, and thereby always returns to a know position upon loss of power.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: September 15, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Terrance Gus McDonald