Patents Represented by Attorney, Agent or Law Firm James H. Fox
  • Patent number: 4859023
    Abstract: Optical fiber cables have an inner sheath extruded or otherwise applied to surround optical fibers. If the fibers are coupled to the sheath, substantial shrinkage of the sheath during manufacturing induces microbending losses in the optical fibers. The inventive technique involves choosing a sheath material having a low viscoelastic modulus, typically PVC, and the application of tension thereto during or after extrusion that prevents such shrinkage. This approach typically avoids the necessity of including longitudinal compressive strength members in the cable. A filled optical fiber cable having a flexible gel to prevent water entry advantageously uses the present technique.
    Type: Grant
    Filed: September 21, 1981
    Date of Patent: August 22, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Bernard R. Eichenbaum, Manuel R. Santana
  • Patent number: 4858168
    Abstract: A 32-bit adder utilizes an optimal partitioning scheme for improving the 32-bit carry look-ahead. Instead of relying on the powers-of-four partitioning scheme used in prior art adders, the inventive technique uses "double generate" and "double propagate" terms. These represent the generate and propagate functions for two bits. In addition, "double group geneate" and "double group propagate" terms are produced, which represent the generate and propagate terms for a 8-bit groups. In this manner, a partition of 1-bit/8-bit is obtained, rather than the prior art 1-bit/4-bit/16-bit. The critical path is typically shortened from 7 logic levels to 5 logic levels, resulting in faster operation. The double functions are advantageously implemented using logic circuitry having two (or more) outputs per gate.
    Type: Grant
    Filed: February 16, 1988
    Date of Patent: August 15, 1989
    Assignee: American Telephone and Telegraph Company
    Inventor: InSeok S. Hwang
  • Patent number: 4851714
    Abstract: In MOS logic circuits with a non-complementary circuit structure (for example, dynamic CMOS), a prior art logic gate generated only a single output signal. However, the logic tree often implements multiple functions, with one function being contained within another function. With prior art logic, if two or more of these functions are needed as separate available output signals, they have to be implemented in several separate gates. The present invention utilizes intermediate functions within the logic tree, providing gates having multiple outputs. Therefore, the present invention reduces the replication of circuitry, thus reducing circuit device count. The advantages include reduced integrated circuit chip area, speed improvement, and power savings, due to the reduction of device count and the corresponding reduction in wire lengths and output loading, etc.
    Type: Grant
    Filed: December 11, 1987
    Date of Patent: July 25, 1989
    Assignee: American Telephone and Telgraph Company, AT&T Bell Laboratories
    Inventor: InSeok S. Hwang
  • Patent number: 4830976
    Abstract: An integrated circuit comprises a resistor that is formed by doping a semiconductor region that is defined by a layer, typically polysilicon, that also defines the gate electrode of field effect transistors in the integrated circuit. The well-controlled linewidth of features defined in this layer provides for tight resistor tolerance, and also allows the value of the resistor to track changes in other features defined by this layer.
    Type: Grant
    Filed: February 24, 1987
    Date of Patent: May 16, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Bernard L. Morris, Jeffrey J. Nagy, Lawrence A. Walter
  • Patent number: 4823029
    Abstract: An integrated circuit has output buffers whose switching rise and/or fall times are controlled to compensate for process speed and other variations. Therefore, an integrated circuit fabricated by a "fast" process does not generate excessive noise, while integrated circuits fabricated by a "slow" process still obtain adequate speed. A control voltage generated by an on-chip voltage divider network is applied to the gate of a control transistor to provide the compensation.
    Type: Grant
    Filed: June 25, 1987
    Date of Patent: April 18, 1989
    Assignee: American Telephone and Telegraph Company AT&T Bell Laboratories
    Inventor: Thaddeus J. Gabara
  • Patent number: 4821089
    Abstract: Integrated circuits implemented in insulated gate (e.g., CMOS) technology have been protected from electrostatic discharge (ESD) by a metal gate field effect transistor. It has been recognized that a "parasitic" bipolar transistor exists in parallel with the metal gate device. Surprisingly, superior protection is obtained by omitting the metal gate, thereby relying only on the avalanche breakdown of the bipolar device for the opposite-polarity protection. It is postulated that the field effect of the metal gate device undesirably restricted the current flow in the prior art technique. The inventive technique may be advantageously implemented using a diode rather than a transistor as the protective element.
    Type: Grant
    Filed: June 4, 1987
    Date of Patent: April 11, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Laboratories
    Inventor: Mark S. Strauss
  • Patent number: 4814291
    Abstract: Certain devices require a high quality thin (<25 nanometer) dielectric layer formed on a deposited silicon layer. Applications include capacitor dielectrics in dynamic memories and linear devices. In another application, an electrically erasable programmable read only memory (EEPROM) uses an SiO.sub.2 layer between the write gate and the floating gate. The present technique oxidizes amorphous silicon under conditions that suppress grain growth to produce a higher quality oxide than that achieved with conventional furnace oxidation of polysilicon. Rapid thermal oxidation is one method of practicing the technique.
    Type: Grant
    Filed: February 25, 1986
    Date of Patent: March 21, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Sea-Chung Kim, Alvaro Maury, William H. Stinebaugh, Jr.
  • Patent number: 4806999
    Abstract: An integrated circuit has an input pad protected from electrostatic discharge by two diodes located under the periphery of the pad. One of the diodes is typically formed in a n-tub, and the other in a p-tub. The boundary between the tubs is located in a region not overlaid by the exposed portion of the pad in one embodiment. An input resistor is optionally included between the pad and the input circuitry for additional ESD protection.
    Type: Grant
    Filed: September 14, 1987
    Date of Patent: February 21, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventor: Mark S. Strauss
  • Patent number: 4803540
    Abstract: A lead frame for mounting a semiconductor chip in an integrated circuit package incorporates a deformation absorbing member as an integral part of the paddle support arm so that the initial, desired physical and electrical characteristics are unaltered after a forming operation such as paddle downsetting.
    Type: Grant
    Filed: November 24, 1986
    Date of Patent: February 7, 1989
    Assignee: American Telephone and Telegraph Co., AT&T Bell Labs
    Inventors: Harold W. Moyer, Harry R. Scholz
  • Patent number: 4802723
    Abstract: Light guided by an optical fiber is tapped by bending the fiber, and substantially surrounding a portion of the fiber with a tube that couples a portion of the optical energy to a detector. The tube can be bent to increase the efficiency of collection of optical energy. The tube can be tapered to improve coupling to small detectors. The loss introduced by the tap is typically in the range of 0.001 to 1.0 dB, and the collection efficiency is high. The technique can be used for single mode or multimode optical fibers, and the fiber can typically remain coated. A large number of taps, typically several hundred, can be applied or removed without disrupting a signal carried by an optical fiber.
    Type: Grant
    Filed: September 9, 1982
    Date of Patent: February 7, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventor: Calvin M. Miller
  • Patent number: 4800415
    Abstract: A new solid state field effect bipolar device provides for high current gain and low input capacitance, while avoiding the "punch-through" effects that limit the downward scaling of conventional bipolar and field effect devices. The device typically comprises a metallic (e.g. a metal or silicide) emitter, which makes ohmic contact to a semi-insulator; a channel terminal which contacts an inversion layer formed at the interface between the semi-insulator and a semiconductor depletion region; and a collector, which is the semiconductor bulk. The novel device controls the flow of majority carriers from the emitter into the collector by the biasing action of charge in the inversion channel. The technique can be utilized in making a transistor, photodetector, thyristor, controlled optical emitter, and other devices.
    Type: Grant
    Filed: January 22, 1987
    Date of Patent: January 24, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: John G. Simmons, Geoffrey W. Taylor
  • Patent number: 4797720
    Abstract: A two-terminal bidirectional semiconductor switching device comprising a body of silicon semiconductor material having in one portion a five-zone switching element and, in another portion integral therewith, a three-zone bidirectional voltage-sensitive breakdown element, there being means including another portion of the body connecting the three-zone element as a gating element to said five-zone element so as to trigger conduction therein bidirectionally when voltage breakdown occurs in either direction in the three-zone element.
    Type: Grant
    Filed: July 29, 1981
    Date of Patent: January 10, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Richard Lindner, Bertram R. Rex
  • Patent number: 4789825
    Abstract: An integrated circuit includes first and second field effect transistors having differing channel lengths, and a means for comparing the channel currents flowing therethrough. An excessive difference of currents indicates "short channel" effects, which can degrade performance. A signal flag indicating this condition may be provided to a test pad on the chip, or used to disable operation of the integrated circuit, or otherwise used to provide an indication.
    Type: Grant
    Filed: February 25, 1988
    Date of Patent: December 6, 1988
    Assignee: American Telephone and Telegraph Co., AT&T Bell Laboratories
    Inventors: John A. Carelli, Richard A. Pedersen, Robert L. Pritchett
  • Patent number: 4788693
    Abstract: A data bus having a given size (e.g., 32 bits) provides for transfer of information between various logic and memory elements within, or among, one or more integrated circuits. Certain of the information transfers require the full information path, while others use only a portion (e.g., 8 or 16 bit transfers). To expedite the transfers of the smaller size words, a given word is replicated to fill up the full data base. This avoids the necessity of specifying the exact location of the smaller word on the data bus.
    Type: Grant
    Filed: September 30, 1985
    Date of Patent: November 29, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Laurence E. Bays, Walter P. Hays, III
  • Patent number: 4788117
    Abstract: A non-destructive double exposure method of examining photoresist features in section by, e.g., scanning electron microscopy, is described.
    Type: Grant
    Filed: January 28, 1987
    Date of Patent: November 29, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: John D. Cuthbert, Dennis E. Schrope, Tungsheng Yang
  • Patent number: 4773687
    Abstract: A wafer handling technique allows for picking up a wafer from its front side. One or more vacuum ports pull the periphery of the wafer into contact with a ledge raised from a broad surface, providing a friction force that prevents lateral movement of the wafer. A port in the broad surface of the handler flows pressurized gas onto the wafer, thereby preventing contact between the handler and the interior of the wafer. The handler may be sized to be relatively thin, and to cover less than half of the surface of the wafer, thereby allowing for readily loading wafers back-to-back in a furnace boat.
    Type: Grant
    Filed: May 22, 1987
    Date of Patent: September 27, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Technologies, Inc.
    Inventors: Donald R. Bush, Gary J. Reichl
  • Patent number: 4758974
    Abstract: After performing a floating point addition, it is desired to normalize the sum; that is, shift the most significant digit of the mantissa into the left-most digit location, and adjust the exponent accordingly. Prior art techniques required performing the addition before calculating the number of shifts required. The present technique determines an approximate shift from the addends during addition, resulting in a significant time saving.
    Type: Grant
    Filed: January 29, 1985
    Date of Patent: July 19, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Evelyn M. Fields, Ronald L. Freyman, Yehuda Rotblum
  • Patent number: 4754169
    Abstract: In various analog applications, it is desirable to have a known offset voltage at the input of a comparator, operational amplifier, or other type of differential stage. For example, in an ISDN receiver, the use of a desired offset allows for discriminating between signals having different amplitudes. In the present technique, a reference current, derived from a reference voltage (V.sub.ref) and on-chip resistor (R1) is used to set the currents through two input transistors, typically MOS transistors. An offset resistor (R0) in the source lead of one of the transistors produces a voltage drop that sets the offset at an input of the differential stage. The voltage drop across R0 is proportional to (V.sub.ref .times.R0)/R1. Since R0 and R1 are fabricated by the same process, their ratio is independent of temperature, process, etc. Therefore, a well-defined offset is obtained.
    Type: Grant
    Filed: April 24, 1987
    Date of Patent: June 28, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventor: Bernard L. Morris
  • Patent number: 4740992
    Abstract: A transceiver is adapted for communication with another transceiver over a common channel by a technique that allows both transceivers to be identical in manufacture and use. The technique avoids designating one transceiver the "master" and the other the "slave", by relying on random time differences between transmissions during a start-up period that initially establishes communications. The transmissions are typically in multi-bit packets. An example using an optical transceiver having a light emitting diode used for both optical transmission and optical detection is given, wherein the channel is an optical fiber.
    Type: Grant
    Filed: April 29, 1986
    Date of Patent: April 26, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Joseph H. Havens, William T. Jones, David A. Snyder
  • Patent number: 4736119
    Abstract: Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due to the floating input node of complementary inverters causing current to flow briefly before clock pulses arrive. The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node. An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.
    Type: Grant
    Filed: February 4, 1987
    Date of Patent: April 5, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Che-Tsung Chen, Kevin D. Kolwicz, Chin-Jen Lin, Won J. Yoon