Abstract: The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.

Abstract: In a first aspect, a method and an apparatus for processing an image classifies the image content of a portion of the image, and in response thereto, selects between linear interpolation (e.g., cubic) and non-linear interpolation (median) methods to interpolate data points for the portion of the image. In one embodiment, non-linear interpolation is selected if the image content of the portion of the image is bi-level, or if portion of the image includes an edge and lacks a specified measure of correlation along a line. Linear interpolation is used in portions where the image content does not include an identified edge and in portions where there is an identified edge in combination with an identified edge direction or a path of isobrightness.

Abstract: A monolithic photodetector including a photodiode, a precharge MOS transistor, a control MOS transistor, and a read MOS transistor, the photodiode and the precharge transistor being formed in a same substrate of a first conductivity type, the photodiode including a first region of the second conductivity type formed under a second region of the first conductivity type more heavily doped than the substrate, and under a third region of the second conductivity type, more heavily doped than the first region, the second and third regions being separate, the first region forming the source region of the second conductivity type of the precharge MOS transistor, the second and third regions being connected, respectively, to a fixed voltage and to the gate of the control transistor.

Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.

Abstract: A computer memory access controller receives load and store requests from a plurality of parallel execution pipelines and forms queues of store and load addresses. A comparator compares load addresses with store addresses in a store address queue and selects a store before load if an address match is found, but selects a load before a store if no address match is found.

Abstract: A method of forming an isolating wall in a semiconductor substrate of a first conductivity type, including the steps of boring in the substrate separate recesses according to the desired isolating wall contour; filling the recesses with a material containing a dopant of the second conductivity type; and performing an anneal step so that regions of the second conductivity type diffused from neighboring recesses join. A first series of recesses is formed from the upper surface and a second series of recesses is formed from the lower surface. The recesses have a substantially rectangular section, the large dimension of which is perpendicular to the alignment of the recesses and a depth smaller than or equal to the half-thickness of the substrate.

Abstract: Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.

Abstract: An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit sequence or the previously supplied bit sequence. If the previously supplied bit sequence is supplied, no power is utilized in that machine cycle.

Abstract: A MOS power transistor formed in an epitaxial layer of a first conductivity type, the MOS power transistor being formed on the front surface of a heavily-doped substrate of the first conductivity type, including a plurality of alternate drain and source fingers of the second conductivity type separated by a channel, conductive fingers covering each of the source fingers and of the drain fingers, a second metal level connecting all the drain metal fingers and substantially covering the entire source-drain structure. Each source finger includes a heavily-doped area of the first conductivity type in contact with the epitaxial layer and with the corresponding source finger, and the rear surface of the substrate is coated with a source metallization.

Abstract: A register of a processor is set to one value when a host is connected to the processor and to a second value when no host is connected. The processor then starts execution after reading the register contents, and if it finds that the second value is stored it writes a set value to a pointer storage location. When the one value is stored, it leaves the content of the pointer location unaffected.

Abstract: A method for run-length encoding two or more data values, the method comprising: loading the data values into storage by forming a first data string, the data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values; generating a second data string having a data sub-string corresponding to each data sub-string of the first data string, all the bits of each of the data sub-strings of the second data string having a first predetermined value if all the bits of the corresponding data sub-string of the first data string have a second predetermined value and having a third predetermined value if any of the bits of the corresponding data sub-string of the first data string has other than the second predetermined value; starting from a predetermined end of the second data string, counting the number of consecutive bits of the second data spring having the first predetermined value; and dividing the said number by the number of bits in each data sub-strin

Abstract: A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.

Abstract: A computer system has a plurality of parallel execution units for executing instructions with assigned guard indicators, one execution unit including a master guard value store and another execution unit having a shadow guard value store, together with guard ownership circuitry to indicate whether the shadow guard value store owns the current value of the guard indicator and transfer circuitry operable to transfer a guard value from the master store to another execution unit.

Abstract: A system comprises: a first execution unit, a second execution unit and a third execution unit; a first-in-first-out memory arranged to receive a plurality of instructions for the first to third execution units and to output the instructions to the execution units; a memory store for storing at least one instruction for one of the execution units, the at least one instruction being received from the first-in-first-out memory, the first and second execution units being arranged to receive their instructions from the first-in-first-out memory and the third execution unit being arranged to receive the instructions from the memory store, wherein a given instruction for the third execution unit is available to the third execution unit at substantially the same time that the instruction would be available to the first or second execution unit if that instruction was for the first or second execution unit.

Abstract: A computer system for executing instructions predicated on guard indicators included in the instructions. The instructions include normal instructions, which are executed if the guard indicator is true and branch instructions, which are executed if the guard indicator is false. The computer system is operable in a branch shadow mode for comparing the guard indicator of the branch instruction with the guard indicator included in subsequent instructions and for continuing to supply instructions if the guard indicators match and for preventing supply of instructions if the guard indicators do not match. The computer system is also operable to disable the branch shadow mode when the branch instruction has been determined such that the branch is taken or not by resolving the status of the guard indicator.

Abstract: An integrated circuit inductance structure, including a silicon substrate, a planar winding of a conductive track, a resistive layer, not etched under the winding, a dielectric layer between the winding and said resistive layer, and discontinuous conductive sections, individually parallel to a portion of the winding which is the closest and electrically connected to ground and to the more heavily-doped layer.

Abstract: A storage array is described which is specifically adapted to support a specific set of instruction modes of a processor. A first set of storage cells have a write input and a single read output. Second and third sets of storage cells each have a write input and only two read outputs. A fourth set of storage cells each have a write input and only three outputs. All the write inputs are addressable in common by a single write address and the read outputs are individually selectable responsive to a read pointer.

Abstract: A prefetch buffer is described which supports a computer system having a plurality of different instruction modes. The number of storage locations which are read out of the prefetch buffer during each machine cycle is controlled in dependence on the instruction mode. Thus the prefetch buffer allows a number of different instruction modes to be support and hides memory access latency.