Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: A data stream processing device for processing a succession of information datagrams from multiple data streams, each datagram comprising a payload and an identifier identifying the data stream of which the datagram forms part, the device comprising: a storer for storing an indication of which of the data streams are required for use; a memory; and a datagram processor connected to the storer and the memory and arranged for: receiving incoming datagrams, reading the identifiers of received datagrams and thereby identifying the data stream of which each datagram forms part, and storing in the memory received datagrams that form part of a data stream required for use, and if successively received datagrams that form part of a data stream required for use are interspersed by one or more received datagrams that do not form part of a data stream required for use, storing an indication of the spacing between the said successively received datagrams.

Abstract: An error amplifier providing an analog error signal, including an operational amplifier, an output terminal of which controls an active load of discharge of a resistive and capacitive network supplied by a reference current source, and circuitry for copying the reference current in an input resistor, a terminal of which receives a measurement signal and the other terminal of which is connected to a non-inverting input of the operational amplifier, the error signal being available across the resistive and capacitive network.

Abstract: A terminal for generating an electromagnetic field adapted to cooperate with at least one transponder when the transponder enters the electromagnetic field, the terminal including circuitry for determining the distance separating the at least one transponder from the terminal without requiring any transmission from the transponder to the terminal. In one example, the terminal also includes a phase regulation loop that regulates the phase of a signal in an oscillating circuit of the terminal with respect to a reference value.

Abstract: A terminal for generating an electromagnetic field adapted to cooperating with at least one transponder when the latter enters its field, the terminal including an oscillating circuit adapted to receiving a high frequency A.C. excitation voltage, and circuitry for detuning this oscillating circuit with respect to a determined transmission frequency when a transponder is very close to the terminal.

Abstract: A method for modifying the doping level of a doped silicon layer including the steps of coating the silicon layer with a silicide layer made of a refractory metal, and heating the interface region between the silicon and the silicide to a predetermined temperature. The method may be applied to the fabrication of an adjustable resistor or a MOS transistor having an adjustable threshold.

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

Abstract: Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.

Abstract: The present invention relates to a contacting structure on a lightly-doped P-type region of a semiconductor component, this P-type region being positively biased during the on-state operation of said component, including, on the P region a layer of a platinum silicide, or of a metal silicide having with the P-type silicon a barrier height lower than or equal to that of the platinum silicide.

Abstract: A component of an image processor receives at least a portion of one or more reconstructed versions of an image including a causal context of an object pixel of the image, and provides a prediction for the object pixel computed as a weighted sum according to at least one measure of correlation and a weighting policy. A component receives a first prediction of an object pixel and reconstructed versions of an image, and provides a second prediction for the object pixel in accordance with the first prediction for the object pixel and a substantially mean error for the context. A component receives one or more prediction differences versions of the image including a causal context prediction difference of an object prediction difference of the image, and provides a prediction for the object prediction difference computed as a weighted sum according to at least one measure of correlation and a weighting policy.

Abstract: A lateral MOS transistor including a gate and drain and source regions of a first conductivity type formed in a substrate of a second conductivity type connected to a first power supply, wherein a doped buried layer of the first conductivity type extends under said drain region and under a portion of the gate, the buried layer being connected to the gate via a one-way connection.

Abstract: Data stream transfer apparatus for receiving a data stream of data cells at variable time intervals and transmitting data frames at predetermined time intervals, including a receiving apparatus, a buffer memory, a data transfer interface, a central processing unit (CPU), and a memory access unit. The receiving apparatus receives the data cells and stores them in the buffer memory. The data transfer interface transfers data frames out of the apparatus at the predetermined time intervals and generates an indication that the data frame has been transferred. The memory access unit receives data defining a location of a data frame in the buffer memory, accesses the buffer memory to retrieve that data frame and transmits that data frame to the data transfer interface. The CPU, upon receiving the indication, determines a time for transfer of a subsequent data frame, and upon reaching that time, transmits to the memory access unit the location of the subsequent frame in the buffer memory.

Abstract: A digital signal processing system, including an analog-to-digital converter adapted to provide at least n-bit samples to a processor, and range selection circuitry for stepwise adjusting the range of the analog-to-digital converter to the amplitude of an input signal and for shifting the position of the n-bit samples on the processor bus according to the selected range.

Abstract: A circuit is described which allows a scan latch to selectively pass inputs derived from either of two test outputs, e.g. scan test and built-in self-test data, but which does not apply an added delay to a data path when this is instead selected.

Abstract: A method of, and apparatus for, processing the output of a design tool for an integrated circuit, the output relating to a circuit under design. A part of the circuit to be investigated is selected. Information relating to each signal in the selected part of the signal is then selected, and an output containing the selected information for the signals in the selected part of the circuit is generated.

Abstract: A method of automated generation of a set of design data defining a system model from an architecture database which is configured to hold in an electronic storage medium architectural parameters wherein each architectural parameter is defined by a primary key field and a set of fields holding subsidiary data relating to the primary key, the method comprising, reading the primary key for each architectural parameter, generating in an electronic storage medium a structured definition entry of the architectural parameter in an electronically readable format, the structured definition entry being associated with an identification field defining the parameter, and loading the primary key into the identification field and the subsidiary data into the structured definition file, and wherein the structured definition entry takes the form of a programming definition of the architectural parameter in a modelling language.

Abstract: An arbiter for arbitrating between a plurality of requests from a plurality of requesters, said arbiter being arranged to assign an order of priority of said requesters, the requester having the highest priority and which has made a request winning the arbitration, wherein the arbiter determines a new priority for said winning requester, said winner being given a priority different from the lowest priority.

Abstract: An inductance formed in an integrated circuit chip, formed of a plurality of parallel conductive lines, of optimized width, each conductive line being formed in the thickness of at least one insulating layer, these lines being interconnected by at least one perpendicular conductive segment.

Abstract: Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching device, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching device, activatable by the common word line, for cou

Abstract: The present invention relates to a demodulator provided to extract two signals modulated in phase quadrature from an intermediary frequency signal, including two analog-to-digital converters receiving the intermediary frequency signal and clocked in phase opposition by a clock at a frequency smaller than the intermediary frequency, at least equal to the bandwidth of the modulated signals, and such that the central frequency of one of the aliased spectrums of the signal converted into digital is substantially equal to half the clock frequency; and two multipliers respectively receiving the outputs of the analog-to-digital converters and receiving at the same time a sequence of values 1, −1, 1, −1, 1 . . . at the clock rate.