Abstract: An NpR variable bandwidth control system comprises a class of systems specifically designed to control the access to a T1 link by traffic types that require different fractions of the transmission facilities simultaneoulsy. These systems can be incorporated into the software that is used to control DSC based T1 networks for special services. Essentially, wideband messages such as video signals are transmitted one at a time, whereas low bit rate data signals such as voice are transmitted in parallel. Such a form of transmission makes economical sense in the transmitting of such signals. A proportion p is applied to one of the group so that all data is equitably handled.

Abstract: A fiber, with enhanced stimulated Raman scattering for use in light amplification, transmits light wave energy in a single mode. The fiber includes a cylindrical core of light transmitting material doped with a substantial concentration of GeO.sub.2, an inner cladding of light transmitting material doped with a sizable concentration of GeO.sub.2 (but less than the substantial concentration) surrounding the core, and an outer cladding of GeO.sub.2 -free material surrounding the inner cladding.

Abstract: Real-time all-optical multiplication of an n component vector by a large m by m matrix having digital accuracy utilizes an updatable two dimensional spatial light modulator.

Abstract: A non-inverting low power high speed bootstrapped buffer having a depletion mode FET device which senses a rising voltage triggers the bootstrap of a high capacitance node isolated from the input. Heavy output loading can be isolated from the bootstrap node. High resistance devices are used to make a fully static circuit.

Abstract: Fast modulation on a low-power laser beam is transferred to a high-power beam when the high-power beam pumps to depletion the amplification of the low-power beam in a fiber Raman amplifier.

Abstract: A character display arrangement for displaying on a CRT rows of discrete characters. Digital codes represent both character data which identifies character shape and attribute data which identifies the attributes to be applied to displayed characters. The attribute data as received and stored in a display memory is in stack-coded form and relates to serial non-spacing attributes. The attribute and character data is read out from the memory one character row at a time. The character data is fed directly to a row buffer which has a position for each character position. The stack-coded attribute data is fed one group at a time to a pertaining fill register where it is decoded into explicit attribute data and fed to the row buffer to be associated with the character data.

Abstract: An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.

Abstract: In a bit-mapped display system, a logical subsystem for programmable sharing of access to a memory in a computer system among a plurality of system resources wherein various modes of operation are supported by the logic and are programmably selected by the user. The use of display memory is controlled between updating and display accesses to prevent breakup of the video image while said image is being changed.

Abstract: An identification code provided in relief on an object is read in that a radiation beam is obliquely incident on the surface on which the identification code is provided, and in that the identification code is observed by a detection system by means of the shadows thus cast.

Abstract: A communication system is described for the transfer of messages between a source device and a destination device. There is provided an end-around coupled series of storage control sections, it being possible to chain a non-branching series of messages to each section. There is provided a "busy/not-busy" indicator, a pointer mechanism for indicating a current storage control section for each of the devices, and a notification device which enables the source device with a "signal" in order to signal an activity. Suitable control prevents deadlock and also individual starvation situations.

Abstract: A processor system having one or more stations (22, 24, 26) which are interconnected by a general communication network (20). Each station has one or more processors (34, 36). Superprocesses (74, 76, 78) which have one or more processes (80-90) can be executed in the stations. Each superprocess is provided with mail-box space (50, 52, 54) for communication with the environment, in which mail-box space the relevant superprocess and other superprocesses can write but in which only the relevant superprocess itself can read. Processes within the same superprocess have variable data in common, but their register stacks are private. Each mail-box is provided with a filling indicator. In the case of a read operation in an empty mail-box space, a wait signal is issued for the initiating process; write operations in a full mail-box space produce an error signal. There is also provided a job control system for allocating jobs among the stations by way of an application load file.

Abstract: A method of detecting binary information from the pulse-shaped output signal of a CCD uses a varying reference voltage which depends on the amplitude of the last pulse detected, in order to render the detection system immune to pulse distortion as a result of transfer losses in the CCD.

Abstract: A data-processing apparatus having a processor, a read-write memory, a data bus, a program counter, a program memory and an instruction register. There is also a feedback finite-state machine possessing a multibit-wide output whose bits are determined in at least two successive machine cycles. This output is connected to a comparator which has its other input connected to the instruction register. A certain equality condition can invalidate the current instruction so that the latter acts as a rapidly performable dummy (NOP) instruction and a program jump can be performed. In a further expansion another multibit-wide output of the finite-state machine can be coupled to the data bus via a decoding circuit.

Abstract: A time-locking method for stations which form part of a local star network in a multiplex data transmission system in which the exchanges between stations are organized in a single frame permitting the simultaneous writing and reading by way of transmission modules which are connected to the network via a coupler. The method has a first phase during which the forward/return propagation time is measured between each station and the coupler, a second phase during which the stations are synchronized with the master station, and a third phase duration in which the time position of each station is fixed in a time slot reserved for the locking of this station in the multiplex.

Abstract: A buffer memory for an input line of a digital interface serves to adapt input data which exhibit large phase fluctuations with respect to the local clock of the interface to this local clock. To this end it is necessary to write the input data with the associated clock into the buffer, the data being read with the local clock. Depending on the phase shifts, write and read operation are then liable to occur simultaneously in border cases. In order to enable the use of conventional components in spite of the described phenomenon, the buffer memory is composed of a number of storage blocks which each comprise the same number of addresses, the storage blocks normally being cyclically addressed in succession. An address spacing monitoring device ensures that read and write operations are always performed only in different storage blocks, so that they can take place simultaneously.

Abstract: A processor for carrying out a calculation mode from a selected plurality of different modes. The processor includes a clock pulse generator which generates clock pulses in an order for processing subsequent data. A mode circuit is included for detecting a mode declaration instruction. The mode declaration instruction is decoded to select a different clock pulse cycle for each different mode selected. Mode control signals and the selected clock pulse cycle are applied to a control code and borrow management circuit to enable the arithmetic and logic unit to carry out one or more operations of the mode control signals.

Abstract: A programmable counter/timer is responsive to signals on a data line for producing signals on one or more output lines and includes a counter connected to the data line, a comparator connected to said counter for producing a control signal when said counter reaches a stored preselected value, and a qualification unit connected to the comparator, the qualification unit having a register for storing a logic state. The qualification unit is responsive to the control signal and the stored logic state for generating a signal on selected output lines when the counter reaches the predetermined stored value.

Abstract: The invention relates to a single-channel digital communication bus system and to a station for use in such system. Only a single physical interconnection between the stations is present for transferring the data. Bit synchronization is effected either in that the data is self-clocking or by a second, clock lead. The data channel realizes an AND-function. The transmission of a message by a master station is answered by an addressed slave by an acknowledge signal train. The acknowledge signal train has a plurality of bits, inclusive of error protection bits. Error protection may be effected by transmitting a series of mutually identical bits, or by means of a CRC signal subtrain. The acknowledge may be positive, negative or a "no acknowledge" signal train.

Abstract: A data processor unit comprising an instruction register for temporary storing a macro-instruction having at least an opcode part and being supplied thereto, and a control section which comprises a sequencer and a microcode memory connected to each other. In said microcode memory there being stored a number of handlers each comprising a number of micro-instruction words. For each opcode there is provided a dedicated handler. The micro-instruction words of handler forming a microroutine for controlling the execution of at least part of a processor action indicated by the corresponding opcode. A handler being addressed by an address generator included in the sequencer and under control of his appertaining opcode.

Abstract: The code is scanned along at least four non-coincident parallel lines in a bar code reading device. The actual processing is started when a margin of sufficient width is detected. The width of the bar is counted and the width found is used to address a table memory. This results in a width indication for a valid bar and a reset signal for an invalid bar. There is provided an bar counter which counts the bars and which addresses a bar memory in order to store the bar identification therein. When the reset signal is received, the series of bar identification received thus far for the relevant line is invalidated, unless all bars of a complete code have already been received. During validation a check is performed as regards correct contents and possibly correspondence between two potentially correct bar codes found.