Patents Represented by Attorney, Agent or Law Firm James W. Huffman
  • Patent number: 7287147
    Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: October 23, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Lawrence Henry Hudepohl, Darren Miller Jones, Radhika Thekkath, Franz Treue
  • Patent number: 7194599
    Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).
    Type: Grant
    Filed: April 29, 2006
    Date of Patent: March 20, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Lawrence H Hudepohl, Darren M Jones, Radhika Thekkath, Franz Treue
  • Patent number: 7185183
    Abstract: A group of bit set and bit clear instructions are provided for a microprocessor to allow atomic modification of privileged architecture control registers. The bit set and bit clear instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers. Two operands are provided for the instructions, the first designating which of the privileged control registers is to be modified, the second designating a general purpose register that contains a bit mask. The bit set instructions set bits in the designated control register according to bits set in the bit mask. The bit clear instructions clear bits in the designated control register according to bits set in the bit mask. By atomically modifying privileged control registers, a requirement for strict nesting of interrupt routines is eliminated.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: February 27, 2007
    Assignee: MIPS Technologies, Inc.
    Inventor: G. Michael Uhler
  • Patent number: 7181600
    Abstract: A bit mask register is provided within the privileged architecture of a microprocessor. The bit mask register includes a plurality of bits, the bits corresponding to other privileged architecture registers. When a bit in the bit mask register is set, its corresponding privileged architecture register is made read-only accessible when the microprocessor is in user mode. When a bit in the bit mask register is clear, its corresponding privileged architecture register is unavailable when the microprocessor is in user mode. If an instruction executing in user mode requests access to a privileged architecture register, and its corresponding bit in the bit mask register is clear, an exception is generated, allowing a kernel mode operating system to optionally set the corresponding bit in the bit mask register, and provide read-only access to the register.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: February 20, 2007
    Assignee: MIPS Technologies, Inc.
    Inventor: G. Michael Uhler
  • Patent number: 7150630
    Abstract: A computer program for execution on a computing device is provided to cross-train students in language development skills such as letter-word correspondence, word recognition, vocabulary, and sentence and paragraph comprehension. A set of programs provide an adaptive methodology for training a student in decoding (semantic, syntactic, phonological, and morphological relationships), knowledge of rhymes, synonyms, antonyms, and homophones, spelling, letter-word correspondences, sentence comprehension, grammatical comprehension, working memory, vocabulary, paragraph comprehension, and improved reading comprehension. In each program, students are presented with an animated scene that poses a question, and a set of answers. The set of answers contain a correct response, and a number of incorrect responses or foils. The student advances to more complex levels by satisfying predetermined correct thresholds. Through repetition and intensity, the student's language skills are developed.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: December 19, 2006
    Assignee: Scientific Learning Corporation
    Inventors: Elizabeth H. Budra, Elizabeth C. Cottle, Logan E. De Ley, Jefferson A. Dewey, William M. Jenkins, Virginia A. Mann, Steven L. Miller
  • Patent number: 7101185
    Abstract: A computer program for execution on a computing device is provided to cross-train students in language development skills such as letter-word correspondence, word recognition, vocabulary, and sentence and paragraph comprehension. A set of programs provide an adaptive methodology for training a student in decoding (semantic, syntactic, phonological, and morphological relationships), knowledge of rhymes, synonyms, antonyms, and homophones, spelling, letter-word correspondences, sentence comprehension, grammatical comprehension, working memory, vocabulary, paragraph comprehension, and improved reading comprehension. In each program, students are presented with an animated scene that poses a question, and a set of answers. The set of answers contain a correct response, and a number of incorrect responses or foils. The student advances to more complex levels by satisfying predetermined correct thresholds. Through repetition and intensity, the student's language skills are developed.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: September 5, 2006
    Assignee: Scientific Learning Corporation
    Inventors: Elizabeth H. Budra, Elizabeth C. Cottle, Logan E. De Ley, Jefferson A. Dewey, William M. Jenkins, Virginia A. Mann, Steven L. Miller
  • Patent number: 7103064
    Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: September 5, 2006
    Assignee: NextIO Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7020879
    Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: March 28, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
  • Patent number: 7000095
    Abstract: A method and apparatus for overlaying hazard clearing with a jump instruction within a pipeline microprocessor is described. The apparatus includes hazard logic to detect when a jump instruction specifies that hazards are to be cleared as part of a jump operation. If hazards are to be cleared, the hazard logic disables branch prediction for the jump instruction, thereby causing the jump instruction to proceed down the pipeline until it is finally resolved, and flushing the pipeline behind the jump instruction. Disabling of branch prediction for the jump instruction effectively clears all execution and/or instruction hazards that preceded the jump instruction. Alternatively, hazard logic causes issue control logic to stall the jump instruction for n-cycles until all hazards are cleared. State tracking logic may be provided to determine whether any instructions are executing in the pipeline that create hazards. If so, hazard logic performs normally.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: February 14, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Niels Gram Jeppesen, G. Michael Uhler
  • Patent number: 6986663
    Abstract: A computer program for execution on a computing device is provided to cross-train students in language development skills such as letter-word correspondence, word recognition, vocabulary, and sentence and paragraph comprehension. A set of programs provide an adaptive methodology for training a student in decoding (semantic, syntactic, phonological, and morphological relationships), knowledge of rhymes, synonyms, antonyms, and homophones, spelling, letter-word correspondences, sentence comprehension, grammatical comprehension, working memory, vocabulary, paragraph comprehension, and improved reading comprehension. In each program, students are presented with an animated scene that poses a question, and a set of answers. The set of answers contain a correct response, and a number of incorrect responses or foils. The student advances to more complex levels by satisfying predetermined correct thresholds. Through repetition and intensity, the student's language skills are developed.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: January 17, 2006
    Assignee: Scientific Learning Corporation
    Inventors: Elizabeth H. Budra, Elizabeth C. Cottle, Logan E. De Ley, Jefferson A. Dewey, William M. Jenkins, Virginia A. Mann, Steven L. Miller
  • Patent number: 6976178
    Abstract: An apparatus and method are provided that disassociates the power consumed by a processing system from the instructions that it executes. The apparatus includes a power predictor that predicts the power that will be consumed by the processing system during execution of particular instructions, and a subsystem inhibition control, that selectively turns on/off available subsystems within the processing system based on the power that is predicted to be consumed. By predicting the power that will be consumed during execution, and by selectively turning on/off particular subsystems, the total power consumed by the processing system can be made invariant, or random. In either case, a counterweight current can be added to the processing system, depending on which of the subsystems are available to be turned on/off, and which are turned on/off, to further disassociate the total power consumed by the processing system from the instructions it is executing.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: December 13, 2005
    Assignee: MIPS Technologies, Inc.
    Inventor: Kevin D. Kissell
  • Patent number: 6961819
    Abstract: A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages within the processing system to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: November 1, 2005
    Assignee: MIPS Technologies, Inc.
    Inventors: Gideon D. Intrater, Anders M. Jagd, Ryan C. Kinter
  • Patent number: 6834024
    Abstract: A multi-ported register cell that reduces the number of metal wires and/or transistors per write port. The cell includes a storage element that stores a bit. Each write port includes three transistors and two wires. The first transistor is coupled to a true input of the storage element. The second transistor is coupled to a complement input of the storage element. The first wire selectively turns on the first and second transistors of one of the ports. The second wire provides the update value. The third transistor selectively couples the second transistor to ground depending upon whether the second wire turns on the third transistor, thereby providing a complement of the update value to the second transistor. The cell also includes one or more read ports for reading the storage element bit. A multi-ported register file may be created from the cells.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: December 21, 2004
    Assignee: IP-First, LLC
    Inventor: Gene K. Frydel
  • Patent number: 6832296
    Abstract: A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string instruction prefix. The programmer specifies the count of cache lines to be prefetched in the ECX register, similarly to the repeat count of a REP string instruction. The effective address of the first cache line is specified similar to the conventional PREFETCH instruction. The REP PREFETCH instruction stops if the address of the current prefetch cache line misses in the TLB, or if the current processor level changes. Additionally, a line is prefetched only if the number of free response buffers is above a programmable threshold. The prefetches are performed at a lower priority than other activities needing access to the cache or TLB.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: December 14, 2004
    Assignee: IP-First, LLC
    Inventor: Rodney E. Hooker
  • Patent number: 6828827
    Abstract: A complementary input dynamic logic circuit for evaluating a complex logic function including complementary input dynamic logic circuits, P-channel devices, an inverter/driver for providing an inverted clock signal, and N-channel pass devices. Each complementary input dynamic logic circuit determines a complementary AND function for a corresponding one of multiple sets of AND terms and indicates the complementary AND function via a corresponding one of multiple preliminary evaluation nodes. The P-channel devices are coupled in series between a source voltage and an output evaluation node. Each series-coupled P-channel device has a gate coupled to a corresponding preliminary evaluation node. The N-channel pass devices are coupled in parallel between the output evaluation node and the inverter/driver. Each N-channel pass device has a gate coupled to a corresponding preliminary evaluation node.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: December 7, 2004
    Assignee: IP-First, LLC
    Inventors: Mir Azam, Raymond A. Bertram
  • Patent number: 6823444
    Abstract: A branch control apparatus in a microprocessor. The branch control apparatus includes an instruction buffer having a plurality of stages that buffer cache lines of instruction bytes received from an instruction cache. A multiplexer selects one of the bottom three stages in the instruction buffer to provide to instruction format logic. The multiplexer selects a stage based on a branch indicator, an instruction wrap indicator, and a carry indicator. The branch indicator indicates whether the processor previously branched to a target address provided by a branch target address cache. The branch indicator and target address are previously stored in association with the stage containing the branch instruction for which the target address is cached. The wrap indicator indicates whether the currently formatted instruction wraps across two cache lines. The carry indicator indicates whether the current instruction being formatted occupies the last byte of the currently formatted instruction buffer stage.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: November 23, 2004
    Assignee: IP-First, LLC
    Inventors: G. Glenn Henry, Thomas C. McDonald
  • Patent number: 6810466
    Abstract: A microprocessor that selectively performs prefetch instructions based upon an indication of future processor bus activity and cache line status. The microprocessor includes a programmable threshold register for storing a threshold value. The threshold value is such that if the depth of bus requests queued in the bus interface unit of the microprocessor is greater than the threshold value, this condition indicates a high likelihood of a high level of bus activity in the near future, for example due to a workload change. If a prefetch instruction cache line address misses in the processor cache, then the line is not prefetched from external memory unless the line may be supplied from one level of internal cache to a lower level of internal cache. However, even in this case the line is not transferred internally if the line status is shared.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: October 26, 2004
    Assignee: IP-First, LLC
    Inventors: G. Glenn Henry, Rodney E. Hooker
  • Patent number: 6791564
    Abstract: A mechanism for, and method of, clipping a red-green-blue (RGB) integer value to an n-bit maximum value and a processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a multiplexer having a first input that accepts n low-order bits of the RGB integer value and a select input that accepts at least one high-order bit of the RGB integer value and (2) an n-bit maximum value generator, coupled to a second input of the multiplexer, that provides the n-bit maximum value to the second input, an output of the multiplexer providing the n low-order bits when the at least one high order bit has a zero value and providing the n-bit maximum value when the at least one high order bit has a nonzero value.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: September 14, 2004
    Assignee: IPFirst, LLC
    Inventors: Timothy A. Elliott, G. Glenn Henry
  • Patent number: 6789100
    Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: September 7, 2004
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
  • Patent number: 6754810
    Abstract: An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: June 22, 2004
    Assignee: I.P.-First, L.L.C.
    Inventors: Timothy A. Elliott, G. Glenn Henry