Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The interface groups signals that together comprises all the necessary information for a coprocessor to issue and execute instructions. Multiple issue groups are formed where each group supports different types of instructions, such as arithmetic instructions, or data transfer instructions. The coprocessor interface has an instruction transfer signal group for transferring different instructions from the CPU to the multi-issue coprocessor, sequentially or in parallel, an issue group designator for specifying an issue path within the multi-issue coprocessor for execution of the instructions, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instructions, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel.

Abstract: A digital level shifter for driving the input of a scaled P-channel driver device within a voltage shifted range to preclude gate-oxide breakdown of the scaled driver device. The scaled driver device has an output operative within an elevated voltage range, so that the voltage shifted range biases the voltage associated with a logic signal from a lower voltage level to an intermediate level to preclude gate-oxide breakdown and protect the scaled driver device. The digital level shifter is implemented using digital devices thereby avoiding analog bias devices. The digital level shifter and the scaled driver device may be implemented on the same integrated circuit (IC) and fabricated using the same process as core circuitry so that the IC may directly interface external devices operating at elevated voltage levels without damaging the core circuitry or the scaled driver device.

Abstract: A bus interface to a split transaction computing bus having separate address and data portions is provided. The bus interface contains separate address and data interfaces for initiating and tracking out-of-order transactions on either or both of the address or data portions of the computing bus. The bus interface includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the computing bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources.

Abstract: A computer program for execution on a computing device is provided to cross-train students in language development skills such as letter-word correspondence, word recognition, vocabulary, and sentence and paragraph comprehension. A set of programs provide an adaptive methodology for training a student in decoding (semantic, syntactic, phonological, and morphological relationships), knowledge of rhymes, synonyms, antonyms, and homophones, spelling, letter-word correspondences, sentence comprehension, grammatical comprehension, working memory, vocabulary, paragraph comprehension, and improved reading comprehension. In each program, students are presented with an animated scene that poses a question, and a set of answers. The set of answers contain a correct response, and a number of incorrect responses or foils. The student advances to more complex levels by satisfying predetermined correct thresholds. Through repetition and intensity, the student's language skills are developed.

Abstract: An apparatus and method are provided to enable programmable page table accesses in a virtual memory system. The apparatus includes context logic and context configuration logic. The context logic designates an entry within a data structure. The context logic has a plurality of fields, where each of the plurality of fields provides part of a pointer to the entry. The context configuration logic is coupled to the context logic. The context configuration logic prescribes the structure of the each of the plurality of fields. Programming the context configuration logic determines the function by which the context logic derives a useful value from a virtual address associated with an event.

Abstract: An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor. The apparatus computes a speculative result associated with an arithmetic operation, where the arithmetic operation is prescribed by a preceding micro instruction that is yet to generate a result. The apparatus utilizes the speculative result to configure a speculative address operand that is provided to an address-dependent micro instruction. The apparatus includes speculative operand calculation logic and an update forwarding cache. The speculative operand calculation logic performs the arithmetic operation to generate the speculative result prior to when execute logic executes the preceding micro instruction to generate the result.

Abstract: A frequency variation apparatus is provided for use in a hardware-based random number generator. The frequency variation apparatus includes sampling frequency variation logic and a sampling frequency oscillator. The sampling frequency variation logic produces a noise signal that corresponds to parity of two independent and asynchronous oscillatory signals. The sampling frequency oscillator is coupled to the sampling frequency variation logic. The sampling frequency oscillator receives the noise signal, and varies a sampling frequency within the random number generator in accordance with the noise signal.

Abstract: An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a first table, a second table, and selection logic. The first table stores branch histories for a first set of branch instructions where the first branch instructions are categorized within the first table according to a first outcome bias. The second table stores branch histories for a second set of branch instructions, where the second branch instructions are categorized within the second table according to a second outcome bias. The selection logic is coupled to the first and second tables. When a branch instruction is executed by the microprocessor, the selection logic selects a particular branch history to predict the outcome of the branch instruction.

Abstract: A cache coherency system for an on-chip computing bus is provided. The coherency system contains a coherency credit counter within each master device on the on-chip bus for monitoring the resources available on the bus for coherent transactions, a coherency input buffer for storing coherent transactions, and a cache for storing coherent data. The coherency credit counter tracks coherent transactions pending in a memory controller, and delays coherent transactions from being placed on the bus if coherent resources are not available in the memory controller. When resources become available in the memory controller, the memory controller signals the coherency system in each of the master devices. The coherency system is coupled to a split transaction tracking and control to establish transaction ID's for each coherent transaction initiated by its master device, and presents a transaction ID along with an address portion of each coherent transaction.

Abstract: A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base addresses of virtual page numbers as in a conventional TLB, also caches memory address range memory types provided by a memory type unit (MTU). In the case of a hit of a virtual address in the TLB, the TLB provides the memory type along with the page table entry, thereby avoiding the need for a serialized accessed to the MTU using the physical address output by the TLB. Logic which controls a processor bus access necessitated by the virtual address makes use of the memory type output by the TLB sooner than would be available from the MTU in conventional data units. If the MTU is updated, the TLB is flushed to insure consistency of memory type values.

Abstract: An apparatus for forwarding storehit data within a pipelined microprocessor is provided. The apparatus has a plurality of response buffers that receive data from a bus that couples a system memory to the microprocessor and multiplexing and forwarding logic. When a store instruction generates a miss of the microprocessor's instruction cache, the store results are written not only to store buffers for updating the cache, but also to one of the response buffers. The missing cache line implicated by the store miss is requested from the system memory, received into the response buffer, and merged with the store results. The cache is updated with the merged data. However, in addition, storehit conditions with the store results generated by load instructions coming down the pipeline are satisfied from the response buffer. The multiplexing and forwarding logic is capable of forwarding the store results from the response buffer to the pipeline both before and after the missing cache line is received.

Abstract: A processor for reducing solids from a predefined input size to a predefined output size is provided. The processor includes a base, an enclosed cylinder, a pair of rotor assemblies (each driven by its own motor) having a plurality of disk sets, the disk sets having a plurality of hammers thereon. As the rotor assemblies spin, the hammers cause the solids to be reduced. The processor further includes two inlet ports for receiving solid material, and an outlet or discharge port for exiting the reduced solid material. Additionally, the processor includes legs for varying the incline of the inlet ports with respect to the outlet port, vanes to create lift on the inlet port side of the cylinder, flow restrictor plates to restrict solids flow within the cylinder, and baffle plates to prevent material build up within the cylinder.

Abstract: An apparatus and method are provided that enable a central processing unit (CPU) to extend the attributes of virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable of storing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer and extended attributes logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries. Each of the TLB entries has an extended memory attributes index field. The extended attributes logic is coupled to the TLB. The extended attributes logic employs the extended memory attributes index field to access one of a plurality of extended memory attributes registers that is external to the TLB. Contents of the extended memory attributes register prescribe specific extended properties for a corresponding virtual memory page.

Abstract: An apparatus and method are provided for executing a combined compare-and-branch operation in a single integer pipeline microprocessor. Typically, the compare-and-branch operation is specified by two macro instructions. The first macro instruction, a compare macro instruction, directs the microprocessor to compare two operands, resulting in the update of a flags register to describe various attributes of the comparison result. The second macro instruction, a conditional jump macro instruction, directs the microprocessor to examine the flags register and to branch program control to a target address if a prescribed condition is met. The apparatus has translation logic that combines the compare macro instruction and the conditional jump macro instruction into a single compare-and-branch micro instruction. The single compare-and-branch micro instruction directs the microprocessor to make the comparison and to perform a conditional branch based upon a result of the comparison.

Abstract: An apparatus and method are provided that enable a central processing unit (CPU) to extend the protection schemes afforded to virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable providing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer (TLB) and extended protection logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries, where each TLB entry of the plurality of TLB entries has a flags field and an extended flags field. The extended protection logic is coupled to the TLB. The extended protection logic specifies legacy access restrictions according to the flags field, and specifies the extended access restrictions according to the flags field in combination with the extended flags field. Specification of the legacy access restrictions preserves compatibility with a legacy virtual page access protocol.

Abstract: An apparatus and method for training the cognitive and memory systems in a subject is provided. The apparatus and method incorporates a number of different programs to be played by the subject. The programs artificially process selected portions of language elements, called phonemes, so they will be more easily distinguished by the subject, and gradually improves the subject's neurological processing and memory of the elements through repetitive stimulation. The programs continually monitor a subject's ability to distinguish the processed language elements, and adaptively configures the programs to challenge and reward the subject by altering the degree of processing. Through adaptive control and repetition of processed speech elements, and presentation of the speech elements in a creative fashion, a subject's cognitive processing of acoustic events common to speech, and memory of language constructs associated with speech elements are significantly improved.

Abstract: An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor. The apparatus computes a speculative result associated with an arithmetic operation, where the arithmetic operation is prescribed by a preceding micro instruction that is yet to generate a result. The apparatus utilizes the speculative result to configure a speculative address operand that is provided to an address-dependent micro instruction The apparatus includes speculative operand calculation logic and an update forwarding cache. The speculative operand calculation logic performs the arithmetic operation to generate the speculative result prior to when execute logic executes the preceding micro instruction to generate the result.

Abstract: An apparatus and method are provided that disassociates the power consumed by a processing device from the instructions that are executing, on a clock-by-clock basis. The apparatus includes a power predictor that predicts the power that will be consumed by the processing device during execution of particular instructions, and a power counterweight, that adds a counterweight current to the total power consumption of the processing device. By predicting the power that will be consumed during execution, and by adding a counterweight current during instruction execution, the total power consumed is made invariant. In another aspect, a random counterweight generator produces a random counterweight current which is added to the power consumed during instruction execution to disassociate the power consumed from the instructions being executed.

Abstract: A covert surveillance system for viewing images from a remote location is provided. The surveillance system provides a mirror, lens and camera arrangement within a small enclosure that allows full 360 degree pan, tilt, zoom, focus and iris control from a remote location. The system receives control commands such as rotate left, zoom out and tilt down via a radio receiver, and controls the camera accordingly. Images viewed by the camera are transmitted to a remote receiver for display on a monitor, or for recording. Continuous camera rotation is achieved by use of a specialized conductive drum that provides continuous electrical contact between camera signals and camera control. In one embodiment, the surveillance system is mounted in place of a photo detector in a street lamp, making the camera virtually undetectable. In addition, a rotatable directional antenna is included in the surveillance system to allow surveillance at great distances from the system.

Abstract: A virtual set cache that avoids virtual set store miss penalty. During a query pass of a store operation, only the untranslated physical address bits of the store address are used to index the cache array. In one embodiment, the untranslated physical address bits select four virtual sets of cache lines. In parallel with the selection of the four virtual sets, a TLB translates the virtual portion of the store address to a physical address. Comparators compare the tags of all of the virtual sets with the translated physical address to determine if a match occurred. If a match occurs for any of the four virtual sets, even if not the set specified by the original virtual address bits of the store address, the cache indicates a hit. The matching virtual set, way and status are saved and used during the update pass to store the data.