Abstract: An edge controlled output buffer circuit reduces the amplitude of power rail noise while maintaining high switching speed by controlled storage and release of charge at the output using new charge storage and discharge capacitor circuits coupled to the output. An output discharging storage capacitor (C1) is coupled to the high potential power rail (V.sub.CC). A first passgate circuit PSGT1 is coupled between the charge storage capacitor (C1) and the output (V.sub.OUT). A first control circuit (CTR1) is coupled to the control node (m2) of the first passgate circuit (PSGT1) for transient turn on of the first passgate circuit (PSGT1) when the output is still at high potential level during transition from high to low potential level at the output. A second passgate circuit (PSGT2) is coupled between the charge storage capacitor (C1) and the low potential power rail (GND).

Abstract: CMOS output circuit improvements control output signal rise and fall times during transition between high and low potential levels at the output (V.sub.OUT). A plurality of pulldown predriver resistors (R1.sub.N, R2.sub.N, R3.sub.N) are coupled in parallel paths in the pulldown predriver circuit. Respective resistance values slow turn on of the output pulldown driver transistor (N1) for achieving a plurality of different fall times. A plurality of pulldown predriver switch transistors (PS1, PS2, PS3) are respectively coupled in series with the pulldown predriver resistors (R1.sub.N, R2.sub.N, R2.sub.N). The switch transistors (PS1, PS2, PS3) have respective control inputs (V.sub.S1, V.sub.S2, V.sub.S3) for selecting respective parallel paths containing the different pulldown predriver resistors (R1.sub.N, R2.sub.N, R3.sub.N). A plurality of pullup predriver resistors (R1.sub.P, R2.sub.P, R3.sub.P) are coupled in parallel paths in the pullup predriver circuit.

Abstract: In a BiCMOS TTL output buffer circuit, bipolar output pullup and pulldown transistors (Q3,Q4,Q5) source and sink current at an output (V.sub.OUT). A phase splitter transistor (Q2,N4) is coupled to the bipolar output pullup and pulldown transistors for controlling respective conducting states in response to data signals at an input (V.sub.IN) during the active bistate mode of operation. CMOS tristate transistors (P1, ,P2,P4,N2) form a tristate circuit for implementing an inactive tristate mode at the output V.sub.OUT in response to tristate enable signals at a tristate enable input (OE). In order to reduce quiescent input current (I.sub.CC) power dissipation, an input power switch CMOS transistor (NI,N4,P1A) is coupled in the input current path to the high potential power rail (V.sub.CCI). The control gate node of the input power switch CMOS transistor (N1, ,N4,P1A) is coupled to the input (V.sub.IN) to control sourcing of input current (I.sub.

Abstract: In a semiconductor device tape assembly bonding process the fingers of a copper tape are reflow soldered to metal bumps located on the semiconductor device. First, the semiconductor wafer is covered with a conductive film composed of thin layers of aluminum, nickel-vanadium alloy and gold. The bumps are then created by electroplating gold through openings in a photoresist mask. The gold bumps are overcoated with a contolled thickness tin layer and the tin is overcoated with a thin gold anticorrosion layer. The copper assembly tape is coated with a thin gold layer and are lightly pressed against the bumps by means of a thermode. The thermode is quickly heated to a temperature well above the gold-tin eutectic melting temperature and then rapidly cooled. The tin layer on the bump will combine with the adjacent gold to form a liquid phase eutectic which will form and contact both the copper finger and the gold bump. Upon cooling the eutectic melt will solder the finger to the bump.

Abstract: An output buffer circuit (10) delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (V.sub.CCQ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (V.sub.CCN) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (V.sub.CCQ, V.sub.CCN) for reducing V.sub.CC droop in the relatively noisy supply rail (V.sub.CCN) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (V.sub.OUT). A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN).

Abstract: Operational amplifiers are often used in unity gain configurations where the output is fed back to the input. In the noninverting buffer configuration the output is directly connected to the inverting input and the circuit becomes a voltage follower. In many cases, the input stage includes cascode coupled transistors which isolate the current mirror load from the differentially operated input transistors. Such cascode transistors act to increase gain to reduce noise and to increase the power supply rejection ratio. When cascode coupled transistors are employed the frequency compensation capacitor can be isolated from loading effects on the input stage, thus, further enhancing the value of a cascoded input stage. However, when such an operational amplifier is operated as a unity gain device its transient response can suffer. Negative output transitions can result in circuit ringing following the negative output transient steps.

Abstract: A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur. Aluminum diffusion is modified by the presence of the germanium so that channeling and out diffusion are controlled. The control is enhanced when boron is incorporated into the silicon along with the aluminum.

Abstract: A transfer molded plastic package having a cavity for accommodating a semiconductor chip is disclosed. A leadframe assembly process is shown wherein the leadframe finger pattern is provided with a resilient or elastic O-ring bead. Top and bottom housing plates which have dimensions that are larger than the bead form the upper and lower surfaces of the package. These plates can be formed of any suitably rigid material. They may be composed of ceramic in low power devices. For high power operation at least one metal plate can be employed. The chip or chips are connected to the lead frame and, along with the top and bottom plates, is located in a transfer mold. The plates are in registy and located so that their outer edges extend beyond the O-ring bead. The mold cavities include faces which press against the plates which are held apart by the O-ring bead so that the bead is compressed by the mold closure.

Abstract: A circuit for use in connection with tristate output buffers in order to provide concurrently for fast discharge of the output pulldown transistor base and at the same time for building in protection against reverse breakdown in the pulldown transistor. The innovation consists of providing a two discharge paths to ground for the base of the output pullup transistor. A low-capacitance path is activated only while the output buffer is in its active mode. In the preferred embodiment of the invention, this low discharge path consists of two CMOS transistors in series, one of which is controlled by the enable signal input E of the buffer circuit and the other by the data signal input V.sub.IN of the buffer circuit. The other path to ground is available whenever the data signal input V.sub.IN is low, regardless of whether the buffer is in its active or inactive mode.

Abstract: A sample and hold circuit is disclosed in which differentially coupled input stages are multiplexed to drive a common output stage. In this way, a plurality of input stages can be employed wherein the transition between sample and hold modes produces greatly reduced switching transients. The circuit has very high overall gain so that sampling accuracy is improved and a very low current input stage configuration permits the use of small hold capacitors without introducing excessive droop in the hold mode. The differential balance is completed by a dummy hold capacitor which is switched along with the hold capacitor. Both of these capacitors are switched in a virtual ground configuration.

Abstract: Circuit configurations are described for use with split lead leadframes and relatively isolated quiet and noisy power rails to reduce power rail noise and circuit noise. An octal register transceiver circuit incorporates a latch (300) coupled to relatively quiet power rails (42,44) and an output buffer circuit (400) having an input circuit coupled to the latch (300) and relatively quiet power rails (42,44). The output driver transistors (Q433,Q434) of the output buffer circuit (400) are coupled to the relatively noisy output power rails (52,54) to isolate the latch circuit from power rail noise and minimize erroneous operation of the latch. A DC Miller Killer circuit (450) is constructed with delay control components (D456,D457,R460) and an alternative discharge path (R458,D459) to reduce aggravation of power rail noise during operation of DCMK.

Abstract: In an integrated circuit a PNP current mirror can lose its current reflection accuracy when low Beta transistors are involved. Since the conventional PNP transistors can often have low Beta this can become a serious problem particularly with high current gain plural output current mirrors. In the invention a compensation current is fed to the current mirror to increase the PNP transistor base currents as an inverse function of Beta. Several alternative circuit embodiments are also disclosed.

Abstract: A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.

Abstract: An output buffer circuit incorporates a ground bounce blocking circuit which blocks transfer of ground bounce pulses from the output ground lead (GND,PGND) to the output (V.sub.OUT) for protecting quiet outputs tied to a common ground bus. A diode element (SD1,D1,ND1, NSC) is coupled in the sinking current path in series with the primary pulldown transistor element (N1,N1P) between the buffer circuit output (V.sub.OUT) and the ground rail (GND,PGND). The diode element is oriented for passing sinking current to the low potential ground rail and for blocking transfer of ground bounce pulses originating in the ground rail (GND,PGND) to the output. The ground rail may be bifurcated to provide a relatively noisy output ground lead (PGND) and a relatively quiet ground lead (QGND). The primary pulldown transistor element (N1P) is coupled to the relatively noisy output ground lead (PGND).

Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction.

Abstract: A CMOS oscillator integrated circuit in a Pierce crystal oscillator circuit configuration operates at oscillating frequencies over a wide band frequency range. A single inverter stage (I1) is coupled between the oscillator input (OSC IN) and the oscillator output (OSC OUT). An oscillator feedback circuit coupled between the oscillator output and oscillator input incorporates an oscillator crystal (XTAL). A pullup gain network (PNET) provides a plurality of different parallel pullup gain paths between the pullup transistor (P1) of the inverter stage (I1) and the high potential power rail (V.sub.CC). The pullup gain paths have different pullup gain resistances (RP2, RP3, . . . RPN) in the respective pullup gain paths for implementing different amplifying gains (A.sub.N) by the inverter stage (I1). Digitally addressable pullup gain switches (P2, P3, . . . PN) are coupled in respective pullup gain paths for selecting different gain paths and different amplifying gains (A.sub.N).

Abstract: A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along with germanium, which is in sufficient concentration to inhibit impurity diffusion in the silicon epitaxial layer. This inhibition effect has been found to be sufficient to cause the combination of boron and gallium to act as slow diffusers. The result is that the performance of arsenic and antimony, in the creation of buried layers for NPN transistors. Thus, the performance of NPN transistors can be matched for PNP transistors. This means that an IC can be fabricated so that more nearly equal performance NPN and PNP transistors can be fabricated simultaneously in a common substrate.

Abstract: Integrated circuit bonding pads are sealed by a surface passivation coating. The bonding pads are first edge-sealed by means of a first applied passivation coating that overlaps the edges of the bonding pad while leaving the central area uncoated. Then, a sequence of metal layers applied to overlap the open central area of the bonding pad. The layer sequence includes an optional first adherence layer such as aluminum, a barrier metal layer such as titanium-tungsten alloy, and an outer noble metal layer such as gold. Then, a second passivation layer is applied so as to overlap and seal the edges of the sequence of metal layers so as to leave only the central portion of the noble metal layer exposed. Electrical contact to the IC is then made to the exposed noble metal in the conventional manner. With respect to the passivating coatings, either or both can be silicon dioxide overcoated with silicon nitride.

Abstract: A synchronous counter flip flop circuit (20) incorporates a logical AND input circuit (22) having multiple inputs (24) and a first output (25) delivering a first count signal upon concurrence of count logic signals at count logic signal inputs (BIT0-BIT7) with a count enable clock signal at a count enable clock signal input (CET). A count delay circuit (30) is coupled to the first output (25) to provide a second output (32) in parallel with the first output (25) for delivering a delayed second count signal. A logical AND intermediate circuit coupling (34) having first and second inputs coupled respectively to the first and second outputs (25,32) provides a third output (35) delivering a third count signal which is a filtered intermediate terminal count signal (TC). An inverting output buffer circuit (26) provides a final inverted filtered terminal count signal (TC) at the final terminal count output (28).

Abstract: A BICMOS passgate circuit (PSGT3) (PSGT3A) for use in latches and flip-flops incorporates a bipolar output circuit (Q1,Q3) comprising a bipolar pullup transistor element (Q1) and a bipolar pulldown transistor element (Q3) coupled to the passgate output (V.sub.OUT) for transient charging and discharging of load capacitance (C.sub.L) at the passgate output (V.sub.OUT). The bipolar output circuit provides increased sinking and sourcing output drive current and .beta. amplification of sinking and sourcing drive current at the passgate output V.sub.OUT in response to data signals at the passgate intput (V'.sub.IN) in the transparent operating mode. An MOS input logic circuit coupled to the passgate input (V'.sub.IN) includes clock signal inputs (CP,CP) for implementing transparent and blocking operating modes.